^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPIC timer driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Dongsheng Wang <Dongsheng.Wang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Li Yang <leoli@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/mpic_timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FSL_GLOBAL_TIMER 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Clock Ratio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Divide by 64 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Divide by 32 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Divide by 16 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Divide by 8 0x00000000 (Hardware default div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPIC_TIMER_TCR_CLKDIV 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPIC_TIMER_TCR_ROVR_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TIMER_STOP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GTCCR_TOG 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TIMERS_PER_GROUP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MAX_TICKS (~0U >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MAX_TICKS_CASCADE (~0U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TIMER_OFFSET(num) (1 << (TIMERS_PER_GROUP - 1 - num))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct timer_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 gtccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 res0[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 gtbcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 res1[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 gtvpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 res2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 gtdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 res3[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) struct cascade_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 tcr_value; /* TCR register: CASC & ROVR value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) unsigned int cascade_map; /* cascade map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) unsigned int timer_num; /* cascade control timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct timer_group_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct timer_regs __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct mpic_timer timer[TIMERS_PER_GROUP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned int timerfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) unsigned int idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) void __iomem *group_tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static struct cascade_priv cascade_timer[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* cascade timer 0 and 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {0x1, 0xc, 0x1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* cascade timer 1 and 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {0x2, 0x6, 0x2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* cascade timer 2 and 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {0x4, 0x3, 0x3}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static LIST_HEAD(timer_group_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void convert_ticks_to_time(struct timer_group_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) const u64 ticks, time64_t *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *time = (u64)div_u64(ticks, priv->timerfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* the time set by the user is converted to "ticks" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int convert_time_to_ticks(struct timer_group_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) time64_t time, u64 *ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u64 max_value; /* prevent u64 overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) max_value = div_u64(ULLONG_MAX, priv->timerfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (time > max_value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *ticks = (u64)time * (u64)priv->timerfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* detect whether there is a cascade timer available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct mpic_timer *detect_idle_cascade_timer(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct timer_group_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct cascade_priv *casc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int array_size = ARRAY_SIZE(cascade_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) casc_priv = cascade_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) for (i = 0; i < array_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) map = casc_priv->cascade_map & priv->idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (map == casc_priv->cascade_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) num = casc_priv->timer_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) priv->timer[num].cascade_handle = casc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* set timer busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) priv->idle &= ~casc_priv->cascade_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return &priv->timer[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) casc_priv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int set_cascade_timer(struct timer_group_priv *priv, u64 ticks,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct cascade_priv *casc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 tmp_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 rem_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* set group tcr reg for cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) casc_priv = priv->timer[num].cascade_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (!casc_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) tcr = casc_priv->tcr_value |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (casc_priv->tcr_value << MPIC_TIMER_TCR_ROVR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) setbits32(priv->group_tcr, tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) tmp_ticks = div_u64_rem(ticks, MAX_TICKS_CASCADE, &rem_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) out_be32(&priv->regs[num].gtccr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) out_be32(&priv->regs[num].gtbcr, tmp_ticks | TIMER_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) out_be32(&priv->regs[num - 1].gtccr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) out_be32(&priv->regs[num - 1].gtbcr, rem_ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static struct mpic_timer *get_cascade_timer(struct timer_group_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u64 ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct mpic_timer *allocated_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Two cascade timers: Support the maximum time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const u64 max_ticks = (u64)MAX_TICKS * (u64)MAX_TICKS_CASCADE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (ticks > max_ticks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* detect idle timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) allocated_timer = detect_idle_cascade_timer(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) if (!allocated_timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* set ticks to timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ret = set_cascade_timer(priv, ticks, allocated_timer->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return allocated_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static struct mpic_timer *get_timer(time64_t time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct timer_group_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct mpic_timer *timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u64 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) list_for_each_entry(priv, &timer_group_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = convert_time_to_ticks(priv, time, &ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ticks > MAX_TICKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (!(priv->flags & FSL_GLOBAL_TIMER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) timer = get_cascade_timer(priv, ticks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for (i = 0; i < TIMERS_PER_GROUP; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* one timer: Reverse allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) num = TIMERS_PER_GROUP - 1 - i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (priv->idle & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* set timer busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) priv->idle &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* set ticks & stop timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) out_be32(&priv->regs[num].gtbcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ticks | TIMER_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) out_be32(&priv->regs[num].gtccr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) priv->timer[num].cascade_handle = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return &priv->timer[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * mpic_start_timer - start hardware timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @handle: the timer to be started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * It will do ->fn(->dev) callback from the hardware interrupt at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * the 'time64_t' point in the future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void mpic_start_timer(struct mpic_timer *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct timer_group_priv *priv = container_of(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct timer_group_priv, timer[handle->num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) clrbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXPORT_SYMBOL(mpic_start_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * mpic_stop_timer - stop hardware timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @handle: the timer to be stoped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * The timer periodically generates an interrupt. Unless user stops the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void mpic_stop_timer(struct mpic_timer *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct timer_group_priv *priv = container_of(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct timer_group_priv, timer[handle->num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct cascade_priv *casc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) setbits32(&priv->regs[handle->num].gtbcr, TIMER_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) casc_priv = priv->timer[handle->num].cascade_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (casc_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) out_be32(&priv->regs[handle->num].gtccr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) out_be32(&priv->regs[handle->num - 1].gtccr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) out_be32(&priv->regs[handle->num].gtccr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXPORT_SYMBOL(mpic_stop_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * mpic_get_remain_time - get timer time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @handle: the timer to be selected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @time: time for timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * Query timer remaining time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) void mpic_get_remain_time(struct mpic_timer *handle, time64_t *time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct timer_group_priv *priv = container_of(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct timer_group_priv, timer[handle->num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct cascade_priv *casc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u64 ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 tmp_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) casc_priv = priv->timer[handle->num].cascade_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (casc_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) tmp_ticks = in_be32(&priv->regs[handle->num].gtccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) tmp_ticks &= ~GTCCR_TOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) ticks = ((u64)tmp_ticks & UINT_MAX) * (u64)MAX_TICKS_CASCADE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tmp_ticks = in_be32(&priv->regs[handle->num - 1].gtccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ticks += tmp_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ticks = in_be32(&priv->regs[handle->num].gtccr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ticks &= ~GTCCR_TOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) convert_ticks_to_time(priv, ticks, time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) EXPORT_SYMBOL(mpic_get_remain_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * mpic_free_timer - free hardware timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @handle: the timer to be removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Free the timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * Note: can not be used in interrupt context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void mpic_free_timer(struct mpic_timer *handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct timer_group_priv *priv = container_of(handle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct timer_group_priv, timer[handle->num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct cascade_priv *casc_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) mpic_stop_timer(handle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) casc_priv = priv->timer[handle->num].cascade_handle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) free_irq(priv->timer[handle->num].irq, priv->timer[handle->num].dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_lock_irqsave(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (casc_priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tcr = casc_priv->tcr_value | (casc_priv->tcr_value <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MPIC_TIMER_TCR_ROVR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clrbits32(priv->group_tcr, tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) priv->idle |= casc_priv->cascade_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) priv->timer[handle->num].cascade_handle = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) priv->idle |= TIMER_OFFSET(handle->num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) spin_unlock_irqrestore(&priv->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) EXPORT_SYMBOL(mpic_free_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * mpic_request_timer - get a hardware timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @fn: interrupt handler function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @dev: callback function of the data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @time: time for timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * This executes the "request_irq", returning NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * else "handle" on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct mpic_timer *mpic_request_timer(irq_handler_t fn, void *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) time64_t time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mpic_timer *allocated_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (list_empty(&timer_group_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (time < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) allocated_timer = get_timer(time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!allocated_timer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = request_irq(allocated_timer->irq, fn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) IRQF_TRIGGER_LOW, "global-timer", dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mpic_free_timer(allocated_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) allocated_timer->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return allocated_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) EXPORT_SYMBOL(mpic_request_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int timer_group_get_freq(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct timer_group_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (priv->flags & FSL_GLOBAL_TIMER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dn = of_find_compatible_node(NULL, NULL, "fsl,mpic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (dn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) of_property_read_u32(dn, "clock-frequency",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) &priv->timerfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (priv->timerfreq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (priv->flags & FSL_GLOBAL_TIMER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) div = (1 << (MPIC_TIMER_TCR_CLKDIV >> 8)) * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) priv->timerfreq /= div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static int timer_group_get_irq(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct timer_group_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const u32 all_timer[] = { 0, TIMERS_PER_GROUP };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) const u32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int irq_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) p = of_get_property(np, "fsl,available-ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (p && len % (2 * sizeof(u32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) pr_err("%pOF: malformed available-ranges property.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) p = all_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) len = sizeof(all_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) len /= 2 * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (i = 0; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) offset = p[i * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) count = p[i * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (j = 0; j < count; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) irq = irq_of_parse_and_map(np, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (!irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pr_err("%pOF: irq parse and map failed.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /* Set timer idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) priv->idle |= TIMER_OFFSET((offset + j));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) priv->timer[offset + j].irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) priv->timer[offset + j].num = offset + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) irq_index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void timer_group_init(struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) struct timer_group_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) priv = kzalloc(sizeof(struct timer_group_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pr_err("%pOF: cannot allocate memory for group.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (of_device_is_compatible(np, "fsl,mpic-global-timer"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) priv->flags |= FSL_GLOBAL_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) priv->regs = of_iomap(np, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!priv->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) pr_err("%pOF: cannot ioremap timer register address.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (priv->flags & FSL_GLOBAL_TIMER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) priv->group_tcr = of_iomap(np, i++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!priv->group_tcr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) pr_err("%pOF: cannot ioremap tcr address.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret = timer_group_get_freq(np, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pr_err("%pOF: cannot get timer frequency.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) ret = timer_group_get_irq(np, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pr_err("%pOF: cannot get timer irqs.\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) spin_lock_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* Init FSL timer hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (priv->flags & FSL_GLOBAL_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) list_add_tail(&priv->node, &timer_group_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (priv->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) iounmap(priv->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (priv->group_tcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) iounmap(priv->group_tcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static void mpic_timer_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct timer_group_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) list_for_each_entry(priv, &timer_group_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Init FSL timer hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (priv->flags & FSL_GLOBAL_TIMER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) setbits32(priv->group_tcr, MPIC_TIMER_TCR_CLKDIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static const struct of_device_id mpic_timer_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { .compatible = "fsl,mpic-global-timer", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static struct syscore_ops mpic_timer_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .resume = mpic_timer_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int __init mpic_timer_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct device_node *np = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for_each_matching_node(np, mpic_timer_ids)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) timer_group_init(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) register_syscore_ops(&mpic_timer_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (list_empty(&timer_group_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) subsys_initcall(mpic_timer_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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