Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2011-2012, Meador Inge, Mentor Graphics Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Some ideas based on un-pushed work done by Vivek Mahajan, Jason Jin, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Mingkai Hu from Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/ppc-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <asm/mpic_msgr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MPIC_MSGR_REGISTERS_PER_BLOCK	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MPIC_MSGR_STRIDE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MPIC_MSGR_MER_OFFSET		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MSGR_INUSE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MSGR_FREE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static struct mpic_msgr **mpic_msgrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static unsigned int mpic_msgr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) static DEFINE_RAW_SPINLOCK(msgrs_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	out_be32(msgr->mer, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) static inline u32 _mpic_msgr_mer_read(struct mpic_msgr *msgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	return in_be32(msgr->mer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) static inline void _mpic_msgr_disable(struct mpic_msgr *msgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u32 mer = _mpic_msgr_mer_read(msgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	_mpic_msgr_mer_write(msgr, mer & ~(1 << msgr->num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct mpic_msgr *msgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	/* Assume busy until proven otherwise.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	msgr = ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	if (reg_num >= mpic_msgr_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	raw_spin_lock_irqsave(&msgrs_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	msgr = mpic_msgrs[reg_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (msgr->in_use == MSGR_FREE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		msgr->in_use = MSGR_INUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	raw_spin_unlock_irqrestore(&msgrs_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return msgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) EXPORT_SYMBOL_GPL(mpic_msgr_get);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) void mpic_msgr_put(struct mpic_msgr *msgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	raw_spin_lock_irqsave(&msgr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	msgr->in_use = MSGR_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	_mpic_msgr_disable(msgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	raw_spin_unlock_irqrestore(&msgr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) EXPORT_SYMBOL_GPL(mpic_msgr_put);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) void mpic_msgr_enable(struct mpic_msgr *msgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	u32 mer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	raw_spin_lock_irqsave(&msgr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mer = _mpic_msgr_mer_read(msgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	_mpic_msgr_mer_write(msgr, mer | (1 << msgr->num));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	raw_spin_unlock_irqrestore(&msgr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) EXPORT_SYMBOL_GPL(mpic_msgr_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) void mpic_msgr_disable(struct mpic_msgr *msgr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	raw_spin_lock_irqsave(&msgr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	_mpic_msgr_disable(msgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	raw_spin_unlock_irqrestore(&msgr->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) EXPORT_SYMBOL_GPL(mpic_msgr_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* The following three functions are used to compute the order and number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * the message register blocks.  They are clearly very inefficent.  However,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * they are called *only* a few times during device initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static unsigned int mpic_msgr_number_of_blocks(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct device_node *aliases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	aliases = of_find_node_by_name(NULL, "aliases");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	if (aliases) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		char buf[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		for (;;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			snprintf(buf, sizeof(buf), "mpic-msgr-block%d", count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			if (!of_find_property(aliases, buf, NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			count += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static unsigned int mpic_msgr_number_of_registers(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	return mpic_msgr_number_of_blocks() * MPIC_MSGR_REGISTERS_PER_BLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int mpic_msgr_block_number(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct device_node *aliases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	unsigned int index, number_of_blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	char buf[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	number_of_blocks = mpic_msgr_number_of_blocks();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	aliases = of_find_node_by_name(NULL, "aliases");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (!aliases)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	for (index = 0; index < number_of_blocks; ++index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		snprintf(buf, sizeof(buf), "mpic-msgr-block%d", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		prop = of_find_property(aliases, buf, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (node == of_find_node_by_path(prop->value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return index == number_of_blocks ? -1 : index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* The probe function for a single message register block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int mpic_msgr_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	void __iomem *msgr_block_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	int block_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	struct resource rsrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	unsigned int irq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	struct device_node *np = dev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	unsigned int receive_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	const unsigned int *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		dev_err(&dev->dev, "Device OF-Node is NULL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* Allocate the message register array upon the first device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	 * registered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (!mpic_msgrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		mpic_msgr_count = mpic_msgr_number_of_registers();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		dev_info(&dev->dev, "Found %d message registers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 				mpic_msgr_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		mpic_msgrs = kcalloc(mpic_msgr_count, sizeof(*mpic_msgrs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 							 GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		if (!mpic_msgrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 				"No memory for message register blocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	dev_info(&dev->dev, "Of-device full name %pOF\n", np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* IO map the message register block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	of_address_to_resource(np, 0, &rsrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	msgr_block_addr = devm_ioremap(&dev->dev, rsrc.start, resource_size(&rsrc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (!msgr_block_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		dev_err(&dev->dev, "Failed to iomap MPIC message registers");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Ensure the block has a defined order. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	block_number = mpic_msgr_block_number(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	if (block_number < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 			"Failed to find message register block alias\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	dev_info(&dev->dev, "Setting up message register block %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			block_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	/* Grab the receive mask which specifies what registers can receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	 * interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	prop = of_get_property(np, "mpic-msgr-receive-mask", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	receive_mask = (prop) ? *prop : 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	/* Build up the appropriate message register data structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	for (i = 0, irq_index = 0; i < MPIC_MSGR_REGISTERS_PER_BLOCK; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		struct mpic_msgr *msgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		unsigned int reg_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		msgr = kzalloc(sizeof(struct mpic_msgr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		if (!msgr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			dev_err(&dev->dev, "No memory for message register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		msgr->in_use = MSGR_FREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		msgr->num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		raw_spin_lock_init(&msgr->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		if (receive_mask & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			msgr->irq = irq_of_parse_and_map(np, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			if (!msgr->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 						"Missing interrupt specifier");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				kfree(msgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 				return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			irq_index += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 			msgr->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		mpic_msgrs[reg_number] = msgr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		mpic_msgr_disable(msgr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		dev_info(&dev->dev, "Register %d initialized: irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 				reg_number, msgr->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct of_device_id mpic_msgr_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.compatible = "fsl,mpic-v3.1-msgr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.data = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct platform_driver mpic_msgr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.name = "mpic-msgr",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.of_match_table = mpic_msgr_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.probe = mpic_msgr_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static __init int mpic_msgr_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	return platform_driver_register(&mpic_msgr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) subsys_initcall(mpic_msgr_init);