Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * IPIC private definitions and structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright 2005 Freescale Semiconductor, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __IPIC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __IPIC_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/ipic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NR_IPIC_INTS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* External IRQS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IPIC_IRQ_EXT0 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IPIC_IRQ_EXT1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IPIC_IRQ_EXT7 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Default Priority Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IPIC_PRIORITY_DEFAULT 0x05309770
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* System Global Interrupt Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define	SICFR_IPSA	0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define	SICFR_IPSB	0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define	SICFR_IPSC	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define	SICFR_IPSD	0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define	SICFR_MPSA	0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define	SICFR_MPSB	0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* System External Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define	SEMSR_SIRQ0	0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* System Error Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SERCR_MCPR	0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct ipic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	volatile u32 __iomem	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	/* The remapper for this IPIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	struct irq_domain		*irqhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct ipic_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	u8	ack;		/* pending register offset from base if the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				   supports ack operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	u8	mask;		/* mask register offset from base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	u8	prio;		/* priority register offset from base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	u8	force;		/* force register offset from base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	u8	bit;		/* register bit position (as per doc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 				   bit mask = 1 << (31 - bit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	u8	prio_mask;	/* priority mask value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #endif /* __IPIC_H__ */