^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * arch/powerpc/sysdev/ipic.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * IPIC routines implementations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2005 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/reboot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fsl_devices.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/ipic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "ipic.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct ipic * primary_ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static struct irq_chip ipic_level_irq_chip, ipic_edge_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static DEFINE_RAW_SPINLOCK(ipic_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static struct ipic_info ipic_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) .prio_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .prio_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .prio_mask = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .prio_mask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .prio_mask = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [6] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .prio_mask = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [7] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .prio_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) [8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .prio = IPIC_SIPRR_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .prio_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) [9] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .prio_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) [10] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .prio_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) [11] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .prio_mask = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .prio_mask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [13] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .bit = 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .prio_mask = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [14] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .bit = 29,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .prio_mask = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [15] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .prio_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .prio = IPIC_SIPRR_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .bit = 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .prio_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [17] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .prio_mask = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [18] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .prio_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [19] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .prio_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) [20] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .prio_mask = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [21] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .prio_mask = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [22] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .prio_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) [23] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .prio_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) [32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .prio_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) [33] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .prio_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [34] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .prio_mask = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) [35] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .prio_mask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [36] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .prio_mask = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) [37] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .prio_mask = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) [38] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .prio_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) [39] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .prio = IPIC_SIPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .prio_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [40] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .prio_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) [41] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .prio_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) [42] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .prio_mask = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) [43] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .prio_mask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [44] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .prio_mask = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [45] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .prio_mask = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [46] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .prio_mask = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) [47] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .mask = IPIC_SIMSR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .prio = IPIC_SIPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .force = IPIC_SIFCR_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .prio_mask = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [48] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .ack = IPIC_SEPNR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .mask = IPIC_SEMSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .force = IPIC_SEFCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .prio_mask = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .prio_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [65] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .prio_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [66] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .prio_mask = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [67] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .prio = IPIC_SMPRR_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .bit = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .prio_mask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [68] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .prio_mask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [69] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .bit = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .prio_mask = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [70] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .bit = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .prio_mask = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [71] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .prio = IPIC_SMPRR_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .bit = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .prio_mask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [72] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [73] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .bit = 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [74] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .bit = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [75] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .bit = 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [76] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [77] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .bit = 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) [78] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .bit = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) [79] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .bit = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [80] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) [81] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .bit = 17,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) [82] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .bit = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [83] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .bit = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [84] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .bit = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [85] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .bit = 21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [86] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .bit = 22,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) [87] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .bit = 23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [88] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) [89] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .bit = 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) [90] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .bit = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) [91] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .bit = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [94] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .mask = IPIC_SIMSR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .prio = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .force = IPIC_SIFCR_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .bit = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static inline u32 ipic_read(volatile u32 __iomem *base, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return in_be32(base + (reg >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline void ipic_write(volatile u32 __iomem *base, unsigned int reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) out_be32(base + (reg >> 2), value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static inline struct ipic * ipic_from_irq(unsigned int virq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return primary_ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static void ipic_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct ipic *ipic = ipic_from_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int src = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) raw_spin_lock_irqsave(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) temp = ipic_read(ipic->regs, ipic_info[src].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) temp |= (1 << (31 - ipic_info[src].bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ipic_write(ipic->regs, ipic_info[src].mask, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) raw_spin_unlock_irqrestore(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static void ipic_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct ipic *ipic = ipic_from_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) unsigned int src = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) raw_spin_lock_irqsave(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) temp = ipic_read(ipic->regs, ipic_info[src].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) temp &= ~(1 << (31 - ipic_info[src].bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ipic_write(ipic->regs, ipic_info[src].mask, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* mb() can't guarantee that masking is finished. But it does finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * for nearly all cases. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) raw_spin_unlock_irqrestore(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static void ipic_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct ipic *ipic = ipic_from_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) unsigned int src = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) raw_spin_lock_irqsave(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) temp = 1 << (31 - ipic_info[src].bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ipic_write(ipic->regs, ipic_info[src].ack, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* mb() can't guarantee that ack is finished. But it does finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * for nearly all cases. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) raw_spin_unlock_irqrestore(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static void ipic_mask_irq_and_ack(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct ipic *ipic = ipic_from_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int src = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) raw_spin_lock_irqsave(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) temp = ipic_read(ipic->regs, ipic_info[src].mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) temp &= ~(1 << (31 - ipic_info[src].bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ipic_write(ipic->regs, ipic_info[src].mask, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) temp = 1 << (31 - ipic_info[src].bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ipic_write(ipic->regs, ipic_info[src].ack, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* mb() can't guarantee that ack is finished. But it does finish
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) * for nearly all cases. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) raw_spin_unlock_irqrestore(&ipic_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct ipic *ipic = ipic_from_irq(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int src = irqd_to_hwirq(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int vold, vnew, edibit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (flow_type == IRQ_TYPE_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) flow_type = IRQ_TYPE_LEVEL_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /* ipic supports only low assertion and high-to-low change senses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (!(flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) printk(KERN_ERR "ipic: sense type 0x%x not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* ipic supports only edge mode on external interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if ((flow_type & IRQ_TYPE_EDGE_FALLING) && !ipic_info[src].ack) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) printk(KERN_ERR "ipic: edge sense not supported on internal "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "interrupts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) irqd_set_trigger_type(d, flow_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (flow_type & IRQ_TYPE_LEVEL_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) irq_set_handler_locked(d, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) d->chip = &ipic_level_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) irq_set_handler_locked(d, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) d->chip = &ipic_edge_irq_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* only EXT IRQ senses are programmable on ipic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * internal IRQ senses are LEVEL_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (src == IPIC_IRQ_EXT0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) edibit = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (src >= IPIC_IRQ_EXT1 && src <= IPIC_IRQ_EXT7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) edibit = (14 - (src - IPIC_IRQ_EXT1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return (flow_type & IRQ_TYPE_LEVEL_LOW) ? 0 : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) vold = ipic_read(ipic->regs, IPIC_SECNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if ((flow_type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_FALLING) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) vnew = vold | (1 << edibit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) vnew = vold & ~(1 << edibit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (vold != vnew)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ipic_write(ipic->regs, IPIC_SECNR, vnew);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return IRQ_SET_MASK_OK_NOCOPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* level interrupts and edge interrupts have different ack operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static struct irq_chip ipic_level_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .name = "IPIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .irq_unmask = ipic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .irq_mask = ipic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .irq_mask_ack = ipic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .irq_set_type = ipic_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static struct irq_chip ipic_edge_irq_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .name = "IPIC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .irq_unmask = ipic_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .irq_mask = ipic_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .irq_mask_ack = ipic_mask_irq_and_ack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .irq_ack = ipic_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .irq_set_type = ipic_set_irq_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int ipic_host_match(struct irq_domain *h, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) enum irq_domain_bus_token bus_token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Exact match, unless ipic node is NULL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct device_node *of_node = irq_domain_get_of_node(h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return of_node == NULL || of_node == node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int ipic_host_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct ipic *ipic = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) irq_set_chip_data(virq, ipic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) irq_set_chip_and_handler(virq, &ipic_level_irq_chip, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /* Set default irq type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) irq_set_irq_type(virq, IRQ_TYPE_NONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static const struct irq_domain_ops ipic_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .match = ipic_host_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .map = ipic_host_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .xlate = irq_domain_xlate_onetwocell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct ipic * __init ipic_init(struct device_node *node, unsigned int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct ipic *ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 temp = 0, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = of_address_to_resource(node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ipic = kzalloc(sizeof(*ipic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ipic == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ipic->irqhost = irq_domain_add_linear(node, NR_IPIC_INTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) &ipic_host_ops, ipic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (ipic->irqhost == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) kfree(ipic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ipic->regs = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* init hw */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ipic_write(ipic->regs, IPIC_SICNR, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* default priority scheme is grouped. If spread mode is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) * configure SICFR accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (flags & IPIC_SPREADMODE_GRP_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) temp |= SICFR_IPSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (flags & IPIC_SPREADMODE_GRP_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) temp |= SICFR_IPSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (flags & IPIC_SPREADMODE_GRP_C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) temp |= SICFR_IPSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (flags & IPIC_SPREADMODE_GRP_D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) temp |= SICFR_IPSD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (flags & IPIC_SPREADMODE_MIX_A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) temp |= SICFR_MPSA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (flags & IPIC_SPREADMODE_MIX_B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) temp |= SICFR_MPSB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ipic_write(ipic->regs, IPIC_SICFR, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /* handle MCP route */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (flags & IPIC_DISABLE_MCP_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) temp = SERCR_MCPR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ipic_write(ipic->regs, IPIC_SERCR, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* handle routing of IRQ0 to MCP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) temp = ipic_read(ipic->regs, IPIC_SEMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (flags & IPIC_IRQ0_MCP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) temp |= SEMSR_SIRQ0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) temp &= ~SEMSR_SIRQ0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ipic_write(ipic->regs, IPIC_SEMSR, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) primary_ipic = ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) irq_set_default_host(primary_ipic->irqhost);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) printk ("IPIC (%d IRQ sources) at %p\n", NR_IPIC_INTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) primary_ipic->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) void ipic_set_default_priority(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ipic_write(primary_ipic->regs, IPIC_SIPRR_A, IPIC_PRIORITY_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ipic_write(primary_ipic->regs, IPIC_SIPRR_B, IPIC_PRIORITY_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ipic_write(primary_ipic->regs, IPIC_SIPRR_C, IPIC_PRIORITY_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ipic_write(primary_ipic->regs, IPIC_SIPRR_D, IPIC_PRIORITY_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ipic_write(primary_ipic->regs, IPIC_SMPRR_A, IPIC_PRIORITY_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ipic_write(primary_ipic->regs, IPIC_SMPRR_B, IPIC_PRIORITY_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 ipic_get_mcp_status(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return primary_ipic ? ipic_read(primary_ipic->regs, IPIC_SERSR) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) void ipic_clear_mcp_status(u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ipic_write(primary_ipic->regs, IPIC_SERSR, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Return an interrupt vector or 0 if no interrupt is pending. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) unsigned int ipic_get_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) BUG_ON(primary_ipic == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define IPIC_SIVCR_VECTOR_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) irq = ipic_read(primary_ipic->regs, IPIC_SIVCR) & IPIC_SIVCR_VECTOR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (irq == 0) /* 0 --> no irq is pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return irq_linear_revmap(primary_ipic->irqhost, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 sicfr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 siprr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 simsr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 sicnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 smprr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 semsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 secnr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 sermr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 sercr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } ipic_saved_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int ipic_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct ipic *ipic = primary_ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ipic_saved_state.sicfr = ipic_read(ipic->regs, IPIC_SICFR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ipic_saved_state.siprr[0] = ipic_read(ipic->regs, IPIC_SIPRR_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ipic_saved_state.siprr[1] = ipic_read(ipic->regs, IPIC_SIPRR_D);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ipic_saved_state.simsr[0] = ipic_read(ipic->regs, IPIC_SIMSR_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) ipic_saved_state.simsr[1] = ipic_read(ipic->regs, IPIC_SIMSR_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ipic_saved_state.sicnr = ipic_read(ipic->regs, IPIC_SICNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ipic_saved_state.smprr[0] = ipic_read(ipic->regs, IPIC_SMPRR_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ipic_saved_state.smprr[1] = ipic_read(ipic->regs, IPIC_SMPRR_B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ipic_saved_state.semsr = ipic_read(ipic->regs, IPIC_SEMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ipic_saved_state.secnr = ipic_read(ipic->regs, IPIC_SECNR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ipic_saved_state.sermr = ipic_read(ipic->regs, IPIC_SERMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ipic_saved_state.sercr = ipic_read(ipic->regs, IPIC_SERCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (fsl_deep_sleep()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* In deep sleep, make sure there can be no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * pending interrupts, as this can cause
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * problems on 831x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ipic_write(ipic->regs, IPIC_SIMSR_H, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ipic_write(ipic->regs, IPIC_SIMSR_L, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ipic_write(ipic->regs, IPIC_SEMSR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ipic_write(ipic->regs, IPIC_SERMR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static void ipic_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct ipic *ipic = primary_ipic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ipic_write(ipic->regs, IPIC_SICFR, ipic_saved_state.sicfr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ipic_write(ipic->regs, IPIC_SIPRR_A, ipic_saved_state.siprr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ipic_write(ipic->regs, IPIC_SIPRR_D, ipic_saved_state.siprr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ipic_write(ipic->regs, IPIC_SIMSR_H, ipic_saved_state.simsr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ipic_write(ipic->regs, IPIC_SIMSR_L, ipic_saved_state.simsr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ipic_write(ipic->regs, IPIC_SICNR, ipic_saved_state.sicnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ipic_write(ipic->regs, IPIC_SMPRR_A, ipic_saved_state.smprr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ipic_write(ipic->regs, IPIC_SMPRR_B, ipic_saved_state.smprr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) ipic_write(ipic->regs, IPIC_SEMSR, ipic_saved_state.semsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ipic_write(ipic->regs, IPIC_SECNR, ipic_saved_state.secnr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ipic_write(ipic->regs, IPIC_SERMR, ipic_saved_state.sermr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ipic_write(ipic->regs, IPIC_SERCR, ipic_saved_state.sercr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define ipic_suspend NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define ipic_resume NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static struct syscore_ops ipic_syscore_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .suspend = ipic_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .resume = ipic_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) static int __init init_ipic_syscore(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (!primary_ipic || !primary_ipic->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) printk(KERN_DEBUG "Registering ipic system core operations\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) register_syscore_ops(&ipic_syscore_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) subsys_initcall(init_ipic_syscore);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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