^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for indirect PCI bridges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 1998 Gabriel Paubert.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/pci-bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int __indirect_read_config(struct pci_controller *hose,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) unsigned char bus_number, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int offset, int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) volatile void __iomem *cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u8 cfg_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 bus_no, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) if (bus_number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) if (devfn != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (ppc_md.pci_exclude_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (ppc_md.pci_exclude_device(hose, bus_number, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) if (bus_number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) cfg_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) bus_no = (bus_number == hose->first_busno) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) hose->self_busno : bus_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) reg = offset & 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Note: the caller has already checked that offset is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * suitably aligned and that len is 1, 2 or 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cfg_data = hose->cfg_data + (offset & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *val = in_8(cfg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *val = in_le16(cfg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *val = in_le32(cfg_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int offset, int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return __indirect_read_config(hose, bus->number, devfn, offset, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int offset, int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pci_controller *hose = pci_bus_to_host(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) volatile void __iomem *cfg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 cfg_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 bus_no, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (bus->number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (devfn != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) if (ppc_md.pci_exclude_device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return PCIBIOS_DEVICE_NOT_FOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (bus->number != hose->first_busno)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) cfg_type = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bus_no = (bus->number == hose->first_busno) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) hose->self_busno : bus->number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (hose->indirect_type & PPC_INDIRECT_TYPE_EXT_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg = ((offset & 0xf00) << 16) | (offset & 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) reg = offset & 0xfc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) (devfn << 8) | reg | cfg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* suppress setting of PCI_PRIMARY_BUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if ((offset == PCI_PRIMARY_BUS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) (bus->number == hose->first_busno))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) val &= 0xffffff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Workaround for PCI_28 Errata in 440EPx/GRx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if ((hose->indirect_type & PPC_INDIRECT_TYPE_BROKEN_MRM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) offset == PCI_CACHE_LINE_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Note: the caller has already checked that offset is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * suitably aligned and that len is 1, 2 or 4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) cfg_data = hose->cfg_data + (offset & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) out_8(cfg_data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) out_le16(cfg_data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) out_le32(cfg_data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return PCIBIOS_SUCCESSFUL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct pci_ops indirect_pci_ops =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .read = indirect_read_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .write = indirect_write_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void setup_indirect_pci(struct pci_controller *hose, resource_size_t cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) resource_size_t cfg_data, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) resource_size_t base = cfg_addr & PAGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __iomem *mbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mbase = ioremap(base, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if ((cfg_data & PAGE_MASK) != base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) hose->ops = &indirect_pci_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) hose->indirect_type = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags