^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * i8259 interrupt controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/i8259.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static volatile void __iomem *pci_intack; /* RO, gives us the irq vector */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static unsigned char cached_8259[2] = { 0xff, 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define cached_A1 (cached_8259[0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define cached_21 (cached_8259[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static DEFINE_RAW_SPINLOCK(i8259_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static struct irq_domain *i8259_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Acknowledge the IRQ using either the PCI host bridge's interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * acknowledge feature or poll. How i8259_init() is called determines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * which is called. It should be noted that polling is broken on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * IBM and Motorola PReP boxes so we must use the int-ack feature on them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) unsigned int i8259_irq(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Either int-ack or poll for the IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) if (pci_intack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) irq = readb(pci_intack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) raw_spin_lock(&i8259_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) lock = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Perform an interrupt acknowledge cycle on controller 1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) outb(0x0C, 0x20); /* prepare for poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) irq = inb(0x20) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (irq == 2 ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Interrupt is cascaded so perform interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * acknowledge on controller 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) outb(0x0C, 0xA0); /* prepare for poll */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) irq = (inb(0xA0) & 7) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (irq == 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * This may be a spurious interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * Read the interrupt status register (ISR). If the most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * significant bit is not set then there is no valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!pci_intack)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) outb(0x0B, 0x20); /* ISR register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if(~inb(0x20) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) } else if (irq == 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) if (lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) raw_spin_unlock(&i8259_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static void i8259_mask_and_ack_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) raw_spin_lock_irqsave(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (d->irq > 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cached_A1 |= 1 << (d->irq-8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) inb(0xA1); /* DUMMY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) outb(cached_A1, 0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) outb(0x20, 0xA0); /* Non-specific EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) outb(0x20, 0x20); /* Non-specific EOI to cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) cached_21 |= 1 << d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) inb(0x21); /* DUMMY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) outb(cached_21, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) outb(0x20, 0x20); /* Non-specific EOI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) raw_spin_unlock_irqrestore(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void i8259_set_irq_mask(int irq_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) outb(cached_A1,0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) outb(cached_21,0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void i8259_mask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pr_debug("i8259_mask_irq(%d)\n", d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) raw_spin_lock_irqsave(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (d->irq < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) cached_21 |= 1 << d->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) cached_A1 |= 1 << (d->irq-8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) i8259_set_irq_mask(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) raw_spin_unlock_irqrestore(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static void i8259_unmask_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) pr_debug("i8259_unmask_irq(%d)\n", d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) raw_spin_lock_irqsave(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (d->irq < 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) cached_21 &= ~(1 << d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) cached_A1 &= ~(1 << (d->irq-8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) i8259_set_irq_mask(d->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) raw_spin_unlock_irqrestore(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct irq_chip i8259_pic = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .name = "i8259",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .irq_mask = i8259_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .irq_disable = i8259_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .irq_unmask = i8259_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .irq_mask_ack = i8259_mask_and_ack_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct resource pic1_iores = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .name = "8259 (master)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .start = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .end = 0x21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .flags = IORESOURCE_IO | IORESOURCE_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static struct resource pic2_iores = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .name = "8259 (slave)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .start = 0xa0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .end = 0xa1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .flags = IORESOURCE_IO | IORESOURCE_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static struct resource pic_edgectrl_iores = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "8259 edge control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .start = 0x4d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .end = 0x4d1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .flags = IORESOURCE_IO | IORESOURCE_BUSY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int i8259_host_match(struct irq_domain *h, struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) enum irq_domain_bus_token bus_token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct device_node *of_node = irq_domain_get_of_node(h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return of_node == NULL || of_node == node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int i8259_host_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pr_debug("i8259_host_map(%d, 0x%lx)\n", virq, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* We block the internal cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (hw == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) irq_set_status_flags(virq, IRQ_NOREQUEST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* We use the level handler only for now, we might want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * be more cautious here but that works for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) irq_set_status_flags(virq, IRQ_LEVEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) irq_set_chip_and_handler(virq, &i8259_pic, handle_level_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int i8259_host_xlate(struct irq_domain *h, struct device_node *ct,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const u32 *intspec, unsigned int intsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) irq_hw_number_t *out_hwirq, unsigned int *out_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static unsigned char map_isa_senses[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) IRQ_TYPE_LEVEL_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) IRQ_TYPE_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) IRQ_TYPE_EDGE_FALLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) IRQ_TYPE_EDGE_RISING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) *out_hwirq = intspec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (intsize > 1 && intspec[1] < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *out_flags = map_isa_senses[intspec[1]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *out_flags = IRQ_TYPE_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct irq_domain_ops i8259_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .match = i8259_host_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .map = i8259_host_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .xlate = i8259_host_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct irq_domain *i8259_get_host(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return i8259_host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * i8259_init - Initialize the legacy controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @node: device node of the legacy PIC (can be NULL, but then, it will match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * all interrupts, so beware)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @intack_addr: PCI interrupt acknowledge (real) address which will return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * the active irq from the 8259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) void i8259_init(struct device_node *node, unsigned long intack_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* initialize the controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) raw_spin_lock_irqsave(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Mask all first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) outb(0xff, 0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) outb(0xff, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* init master interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) outb(0x11, 0x20); /* Start init sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) outb(0x00, 0x21); /* Vector base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) outb(0x04, 0x21); /* edge triggered, Cascade (slave) on IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) outb(0x01, 0x21); /* Select 8086 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* init slave interrupt controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) outb(0x11, 0xA0); /* Start init sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) outb(0x08, 0xA1); /* Vector base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) outb(0x02, 0xA1); /* edge triggered, Cascade (slave) on IRQ2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) outb(0x01, 0xA1); /* Select 8086 mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* That thing is slow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* always read ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) outb(0x0B, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) outb(0x0B, 0xA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* Unmask the internal cascade */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) cached_21 &= ~(1 << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Set interrupt masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) outb(cached_A1, 0xA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) outb(cached_21, 0x21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) raw_spin_unlock_irqrestore(&i8259_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* create a legacy host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) i8259_host = irq_domain_add_legacy_isa(node, &i8259_host_ops, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (i8259_host == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) printk(KERN_ERR "i8259: failed to allocate irq host !\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* reserve our resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* XXX should we continue doing that ? it seems to cause problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * with further requesting of PCI IO resources for that range...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * need to look into it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) request_resource(&ioport_resource, &pic1_iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) request_resource(&ioport_resource, &pic2_iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) request_resource(&ioport_resource, &pic_edgectrl_iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (intack_addr != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) pci_intack = ioremap(intack_addr, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) printk(KERN_INFO "i8259 legacy interrupt controller initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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