Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #ifndef __PPC_FSL_SOC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #define __PPC_FSL_SOC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) struct spi_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extern phys_addr_t get_immrbase(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) extern u32 get_brgfreq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) extern u32 get_baudrate(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static inline u32 get_brgfreq(void) { return -1; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static inline u32 get_baudrate(void) { return -1; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) extern u32 fsl_get_sys_freq(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct spi_board_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct device_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* The different ports that the DIU can be connected to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) enum fsl_diu_monitor_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	FSL_DIU_PORT_DVI,	/* DVI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	FSL_DIU_PORT_LVDS,	/* Single-link LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	FSL_DIU_PORT_DLVDS	/* Dual-link LVDS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct platform_diu_data_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	u32 (*get_pixel_format)(enum fsl_diu_monitor_port port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		unsigned int bpp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	void (*set_gamma_table)(enum fsl_diu_monitor_port port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		char *gamma_table_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	void (*set_monitor_port)(enum fsl_diu_monitor_port port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	void (*set_pixel_clock)(unsigned int pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	enum fsl_diu_monitor_port (*valid_monitor_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		(enum fsl_diu_monitor_port port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	void (*release_bootmem)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) extern struct platform_diu_data_ops diu_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) void __noreturn fsl_hv_restart(char *cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) void __noreturn fsl_hv_halt(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif