^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale MPC85xx/MPC86xx RapidIO RMU support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Sysgo AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Thomas Moll <thomas.moll@sysgo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * - fixed maintenance access routines, check for aligned access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2009 Integrated Device Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Alex Bounine <alexandre.bounine@idt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - Added Port-Write message handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - Added Machine Check exception handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Zhang Wei <wei.zhang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Lian Minghuan-B31939 <Minghuan.Lian@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Liu Gang <Gang.Liu@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright 2005 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Matt Porter <mporter@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "fsl_rio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GET_RMM_HANDLE(mport) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) (((struct rio_priv *)(mport->priv))->rmm_handle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* RapidIO definition irq, which read from OF-tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IRQ_RIO_PW(m) (((struct fsl_rio_pw *)(m))->pwirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IRQ_RIO_BELL(m) (((struct fsl_rio_dbell *)(m))->bellirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IRQ_RIO_TX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->txirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IRQ_RIO_RX(m) (((struct fsl_rmu *)(GET_RMM_HANDLE(m)))->rxirq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RIO_MIN_TX_RING_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RIO_MAX_TX_RING_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define RIO_MIN_RX_RING_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define RIO_MAX_RX_RING_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define RIO_IPWMR_SEN 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RIO_IPWMR_QFIE 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define RIO_IPWMR_EIE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define RIO_IPWMR_CQ 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RIO_IPWMR_PWE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RIO_IPWSR_QF 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define RIO_IPWSR_TE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RIO_IPWSR_QFI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RIO_IPWSR_PWD 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RIO_IPWSR_PWB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RIO_EPWISR 0x10010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* EPWISR Error match value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RIO_EPWISR_PINT1 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RIO_EPWISR_PINT2 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RIO_EPWISR_MU 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RIO_EPWISR_PW 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IPWSR_CLEAR 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OMSR_CLEAR 0x1cb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMSR_CLEAR 0x491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IDSR_CLEAR 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ODSR_CLEAR 0x1c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LTLEECSR_ENABLE_ALL 0xFFC000FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define RIO_LTLEECSR 0x060c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define RIO_IM0SR 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define RIO_IM1SR 0x164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define RIO_OM0SR 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define RIO_OM1SR 0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RIO_DBELL_WIN_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RIO_MSG_OMR_MUI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RIO_MSG_OSR_TE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RIO_MSG_OSR_QOI 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define RIO_MSG_OSR_QFI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define RIO_MSG_OSR_MUB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RIO_MSG_OSR_EOMI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RIO_MSG_OSR_QEI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RIO_MSG_IMR_MI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RIO_MSG_ISR_TE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RIO_MSG_ISR_QFI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RIO_MSG_ISR_DIQI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RIO_MSG_DESC_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RIO_MSG_BUFFER_SIZE 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DOORBELL_DMR_DI 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DOORBELL_DSR_TE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DOORBELL_DSR_QFI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DOORBELL_DSR_DIQI 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DOORBELL_MESSAGE_SIZE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static DEFINE_SPINLOCK(fsl_rio_doorbell_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct rio_msg_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 omr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 osr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 odqdpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 osar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 odpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 odatr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 odcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 odqepar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 pad4[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 imr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 pad5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 ifqdpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 pad6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 ifqepar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct rio_dbell_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 odmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 odsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 pad1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 oddpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 oddatr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 pad2[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 odretcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 pad3[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 dmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 dqdpar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 pad5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 dqepar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct rio_pw_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 pwmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 pwsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 epwqbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 pwqbar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct rio_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 saddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 dport;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 dattr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 pad3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 dwcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 pad4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct rio_msg_tx_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void *virt_buffer[RIO_MAX_TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) dma_addr_t phys_buffer[RIO_MAX_TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) int tx_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) void *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct rio_msg_rx_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void *virt_buffer[RIO_MAX_RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int rx_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void *dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct fsl_rmu {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct rio_msg_regs __iomem *msg_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct rio_msg_tx_ring msg_tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct rio_msg_rx_ring msg_rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) int txirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int rxirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct rio_dbell_msg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u16 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u16 tid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u16 sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u16 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * fsl_rio_tx_handler - MPC85xx outbound message interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @irq: Linux interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @dev_instance: Pointer to interrupt-specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * Handles outbound message interrupts. Executes a register outbound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * mailbox event handler and acks the interrupt occurrence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) fsl_rio_tx_handler(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) int osr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct rio_mport *port = (struct rio_mport *)dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) osr = in_be32(&rmu->msg_regs->osr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (osr & RIO_MSG_OSR_TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) pr_info("RIO: outbound message transmission error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (osr & RIO_MSG_OSR_QOI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pr_info("RIO: outbound message queue overflow\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_QOI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (osr & RIO_MSG_OSR_EOMI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 dqp = in_be32(&rmu->msg_regs->odqdpar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int slot = (dqp - rmu->msg_tx_ring.phys) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (port->outb_msg[0].mcback != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) port->outb_msg[0].mcback(port, rmu->msg_tx_ring.dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Ack the end-of-message interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) out_be32(&rmu->msg_regs->osr, RIO_MSG_OSR_EOMI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * fsl_rio_rx_handler - MPC85xx inbound message interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @irq: Linux interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @dev_instance: Pointer to interrupt-specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * Handles inbound message interrupts. Executes a registered inbound
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * mailbox event handler and acks the interrupt occurrence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) fsl_rio_rx_handler(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct rio_mport *port = (struct rio_mport *)dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct fsl_rmu *rmu = GET_RMM_HANDLE(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) isr = in_be32(&rmu->msg_regs->isr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (isr & RIO_MSG_ISR_TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pr_info("RIO: inbound message reception error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) out_be32((void *)&rmu->msg_regs->isr, RIO_MSG_ISR_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* XXX Need to check/dispatch until queue empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (isr & RIO_MSG_ISR_DIQI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Can receive messages for any mailbox/letter to that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * mailbox destination. So, make the callback with an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * unknown/invalid mailbox number argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (port->inb_msg[0].mcback != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) port->inb_msg[0].mcback(port, rmu->msg_rx_ring.dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Ack the queueing interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) out_be32(&rmu->msg_regs->isr, RIO_MSG_ISR_DIQI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * fsl_rio_dbell_handler - MPC85xx doorbell interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @irq: Linux interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @dev_instance: Pointer to interrupt-specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * Handles doorbell interrupts. Parses a list of registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * doorbell event handlers and executes a matching event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) fsl_rio_dbell_handler(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int dsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct fsl_rio_dbell *fsl_dbell = (struct fsl_rio_dbell *)dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) dsr = in_be32(&fsl_dbell->dbell_regs->dsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (dsr & DOORBELL_DSR_TE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pr_info("RIO: doorbell reception error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (dsr & DOORBELL_DSR_QFI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pr_info("RIO: doorbell queue full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_QFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* XXX Need to check/dispatch until queue empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (dsr & DOORBELL_DSR_DIQI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct rio_dbell_msg *dmsg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) fsl_dbell->dbell_ring.virt +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) (in_be32(&fsl_dbell->dbell_regs->dqdpar) & 0xfff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct rio_dbell *dbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) pr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ("RIO: processing doorbell,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) " sid %2.2x tid %2.2x info %4.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) dmsg->sid, dmsg->tid, dmsg->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) for (i = 0; i < MAX_PORT_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (fsl_dbell->mport[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) list_for_each_entry(dbell,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) &fsl_dbell->mport[i]->dbells, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if ((dbell->res->start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) <= dmsg->info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) && (dbell->res->end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) >= dmsg->info)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (found && dbell->dinb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dbell->dinb(fsl_dbell->mport[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dbell->dev_id, dmsg->sid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dmsg->tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dmsg->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) pr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ("RIO: spurious doorbell,"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) " sid %2.2x tid %2.2x info %4.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) dmsg->sid, dmsg->tid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dmsg->info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) setbits32(&fsl_dbell->dbell_regs->dmr, DOORBELL_DMR_DI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) out_be32(&fsl_dbell->dbell_regs->dsr, DOORBELL_DSR_DIQI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) void msg_unit_error_handler(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /*XXX: Error recovery is not implemented, we just clear errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) out_be32((u32 *)(rmu_regs_win + RIO_IM0SR), IMSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) out_be32((u32 *)(rmu_regs_win + RIO_IM1SR), IMSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) out_be32((u32 *)(rmu_regs_win + RIO_OM0SR), OMSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) out_be32((u32 *)(rmu_regs_win + RIO_OM1SR), OMSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) out_be32(&dbell->dbell_regs->odsr, ODSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) out_be32(&dbell->dbell_regs->dsr, IDSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) out_be32(&pw->pw_regs->pwsr, IPWSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) * fsl_rio_port_write_handler - MPC85xx port write interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * @irq: Linux interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * @dev_instance: Pointer to interrupt-specific data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Handles port write interrupts. Parses a list of registered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * port write event handlers and executes a matching event handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fsl_rio_port_write_handler(int irq, void *dev_instance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u32 ipwmr, ipwsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct fsl_rio_pw *pw = (struct fsl_rio_pw *)dev_instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 epwisr, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) epwisr = in_be32(rio_regs_win + RIO_EPWISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!(epwisr & RIO_EPWISR_PW))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) goto pw_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) ipwmr = in_be32(&pw->pw_regs->pwmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ipwsr = in_be32(&pw->pw_regs->pwsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #ifdef DEBUG_PW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_debug("PW Int->IPWMR: 0x%08x IPWSR: 0x%08x (", ipwmr, ipwsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ipwsr & RIO_IPWSR_QF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) pr_debug(" QF");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (ipwsr & RIO_IPWSR_TE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pr_debug(" TE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (ipwsr & RIO_IPWSR_QFI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pr_debug(" QFI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ipwsr & RIO_IPWSR_PWD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) pr_debug(" PWD");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ipwsr & RIO_IPWSR_PWB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pr_debug(" PWB");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) pr_debug(" )\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Schedule deferred processing if PW was received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ipwsr & RIO_IPWSR_QFI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Save PW message (if there is room in FIFO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * otherwise discard it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (kfifo_avail(&pw->pw_fifo) >= RIO_PW_MSG_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pw->port_write_msg.msg_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) kfifo_in(&pw->pw_fifo, pw->port_write_msg.virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) RIO_PW_MSG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pw->port_write_msg.discard_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) pr_debug("RIO: ISR Discarded Port-Write Msg(s) (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pw->port_write_msg.discard_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Clear interrupt and issue Clear Queue command. This allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * another port-write to be received.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_QFI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) out_be32(&pw->pw_regs->pwmr, ipwmr | RIO_IPWMR_CQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) schedule_work(&pw->pw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if ((ipwmr & RIO_IPWMR_EIE) && (ipwsr & RIO_IPWSR_TE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) pw->port_write_msg.err_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) pr_debug("RIO: Port-Write Transaction Err (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) pw->port_write_msg.err_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Clear Transaction Error: port-write controller should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * disabled when clearing this error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) out_be32(&pw->pw_regs->pwmr, ipwmr & ~RIO_IPWMR_PWE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_TE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) out_be32(&pw->pw_regs->pwmr, ipwmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ipwsr & RIO_IPWSR_PWD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pw->port_write_msg.discard_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) pr_debug("RIO: Port Discarded Port-Write Msg(s) (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) pw->port_write_msg.discard_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) out_be32(&pw->pw_regs->pwsr, RIO_IPWSR_PWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pw_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (epwisr & RIO_EPWISR_PINT1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) fsl_rio_port_error_handler(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (epwisr & RIO_EPWISR_PINT2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fsl_rio_port_error_handler(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (epwisr & RIO_EPWISR_MU) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tmp = in_be32(rio_regs_win + RIO_LTLEDCSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) pr_debug("RIO_LTLEDCSR = 0x%x\n", tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msg_unit_error_handler();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static void fsl_pw_dpc(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct fsl_rio_pw *pw = container_of(work, struct fsl_rio_pw, pw_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) union rio_pw_msg msg_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * Process port-write messages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) while (kfifo_out_spinlocked(&pw->pw_fifo, (unsigned char *)&msg_buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RIO_PW_MSG_SIZE, &pw->pw_fifo_lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #ifdef DEBUG_PW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) pr_debug("%s : Port-Write Message:", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) for (i = 0; i < RIO_PW_MSG_SIZE/sizeof(u32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if ((i%4) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) pr_debug("\n0x%02x: 0x%08x", i*4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msg_buffer.raw[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) pr_debug(" 0x%08x", msg_buffer.raw[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pr_debug("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Pass the port-write message to RIO core for processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 0; i < MAX_PORT_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (pw->mport[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) rio_inb_pwrite_handler(pw->mport[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) &msg_buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * fsl_rio_pw_enable - enable/disable port-write interface init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * @mport: Master port implementing the port write unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * @enable: 1=enable; 0=disable port-write message handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int fsl_rio_pw_enable(struct rio_mport *mport, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) rval = in_be32(&pw->pw_regs->pwmr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rval |= RIO_IPWMR_PWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) rval &= ~RIO_IPWMR_PWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) out_be32(&pw->pw_regs->pwmr, rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * fsl_rio_port_write_init - MPC85xx port write interface init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * @mport: Master port implementing the port write unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * Initializes port write unit hardware and DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * ring. Called from fsl_rio_setup(). Returns %0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * or %-ENOMEM on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int fsl_rio_port_write_init(struct fsl_rio_pw *pw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Following configurations require a disabled port write controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) out_be32(&pw->pw_regs->pwmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) in_be32(&pw->pw_regs->pwmr) & ~RIO_IPWMR_PWE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Initialize port write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) pw->port_write_msg.virt = dma_alloc_coherent(pw->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) RIO_PW_MSG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) &pw->port_write_msg.phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (!pw->port_write_msg.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pr_err("RIO: unable allocate port write queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) pw->port_write_msg.err_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pw->port_write_msg.discard_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Point dequeue/enqueue pointers at first entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) out_be32(&pw->pw_regs->epwqbar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) out_be32(&pw->pw_regs->pwqbar, (u32) pw->port_write_msg.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) pr_debug("EIPWQBAR: 0x%08x IPWQBAR: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) in_be32(&pw->pw_regs->epwqbar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) in_be32(&pw->pw_regs->pwqbar));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Clear interrupt status IPWSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) out_be32(&pw->pw_regs->pwsr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) (RIO_IPWSR_TE | RIO_IPWSR_QFI | RIO_IPWSR_PWD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Configure port write controller for snooping enable all reporting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) clear queue full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) out_be32(&pw->pw_regs->pwmr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) RIO_IPWMR_SEN | RIO_IPWMR_QFIE | RIO_IPWMR_EIE | RIO_IPWMR_CQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Hook up port-write handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) rc = request_irq(IRQ_RIO_PW(pw), fsl_rio_port_write_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) IRQF_SHARED, "port-write", (void *)pw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pr_err("MPC85xx RIO: unable to request inbound doorbell irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Enable Error Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) out_be32((u32 *)(rio_regs_win + RIO_LTLEECSR), LTLEECSR_ENABLE_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) INIT_WORK(&pw->pw_work, fsl_pw_dpc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) spin_lock_init(&pw->pw_fifo_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (kfifo_alloc(&pw->pw_fifo, RIO_PW_MSG_SIZE * 32, GFP_KERNEL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pr_err("FIFO allocation failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) goto err_out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) pr_debug("IPWMR: 0x%08x IPWSR: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) in_be32(&pw->pw_regs->pwmr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) in_be32(&pw->pw_regs->pwsr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) err_out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) free_irq(IRQ_RIO_PW(pw), (void *)pw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dma_free_coherent(pw->dev, RIO_PW_MSG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) pw->port_write_msg.virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pw->port_write_msg.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * fsl_rio_doorbell_send - Send a MPC85xx doorbell message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) * @mport: RapidIO master port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) * @index: ID of RapidIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * @destid: Destination ID of target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * @data: 16-bit info field of RapidIO doorbell message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * Sends a MPC85xx doorbell message. Returns %0 on success or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) int fsl_rio_doorbell_send(struct rio_mport *mport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int index, u16 destid, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) pr_debug("fsl_doorbell_send: index %d destid %4.4x data %4.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) index, destid, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) spin_lock_irqsave(&fsl_rio_doorbell_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* In the serial version silicons, such as MPC8548, MPC8641,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * below operations is must be.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) out_be32(&dbell->dbell_regs->odmr, 0x00000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) out_be32(&dbell->dbell_regs->odretcr, 0x00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) out_be32(&dbell->dbell_regs->oddpr, destid << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) out_be32(&dbell->dbell_regs->oddatr, (index << 20) | data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) out_be32(&dbell->dbell_regs->odmr, 0x00000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) spin_unlock_irqrestore(&fsl_rio_doorbell_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * fsl_add_outb_message - Add message to the MPC85xx outbound message queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * @mport: Master port with outbound message queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * @rdev: Target of outbound message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * @mbox: Outbound mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * @buffer: Message to add to outbound queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * @len: Length of message
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * Adds the @buffer message to the MPC85xx outbound message queue. Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * %0 on success or %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) fsl_add_outb_message(struct rio_mport *mport, struct rio_dev *rdev, int mbox,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) void *buffer, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) u32 omr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct rio_tx_desc *desc = (struct rio_tx_desc *)rmu->msg_tx_ring.virt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) + rmu->msg_tx_ring.tx_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) pr_debug("RIO: fsl_add_outb_message(): destid %4.4x mbox %d buffer " \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "%p len %8.8zx\n", rdev->destid, mbox, buffer, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if ((len < 8) || (len > RIO_MAX_MSG_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Copy and clear rest of buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) memcpy(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot], buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (len < (RIO_MAX_MSG_SIZE - 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) memset(rmu->msg_tx_ring.virt_buffer[rmu->msg_tx_ring.tx_slot]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) + len, 0, RIO_MAX_MSG_SIZE - len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /* Set mbox field for message, and set destid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) desc->dport = (rdev->destid << 16) | (mbox & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Enable EOMI interrupt and priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) desc->dattr = 0x28000000 | ((mport->index) << 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Set transfer size aligned to next power of 2 (in double words) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) desc->dwcnt = is_power_of_2(len) ? len : 1 << get_bitmask_order(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Set snooping and source buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) desc->saddr = 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) | rmu->msg_tx_ring.phys_buffer[rmu->msg_tx_ring.tx_slot];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* Increment enqueue pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) omr = in_be32(&rmu->msg_regs->omr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) out_be32(&rmu->msg_regs->omr, omr | RIO_MSG_OMR_MUI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /* Go to next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (++rmu->msg_tx_ring.tx_slot == rmu->msg_tx_ring.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) rmu->msg_tx_ring.tx_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * fsl_open_outb_mbox - Initialize MPC85xx outbound mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @mport: Master port implementing the outbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * @dev_id: Device specific pointer to pass on event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * @mbox: Mailbox to open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * @entries: Number of entries in the outbound mailbox ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * Initializes buffer ring, request the outbound message interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * and enables the outbound message unit. Returns %0 on success and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * %-EINVAL or %-ENOMEM on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) fsl_open_outb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) int i, j, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if ((entries < RIO_MIN_TX_RING_SIZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (entries > RIO_MAX_TX_RING_SIZE) || (!is_power_of_2(entries))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Initialize shadow copy ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) rmu->msg_tx_ring.dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) rmu->msg_tx_ring.size = entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) for (i = 0; i < rmu->msg_tx_ring.size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) rmu->msg_tx_ring.virt_buffer[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dma_alloc_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) &rmu->msg_tx_ring.phys_buffer[i], GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (!rmu->msg_tx_ring.virt_buffer[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) for (j = 0; j < rmu->msg_tx_ring.size; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (rmu->msg_tx_ring.virt_buffer[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) dma_free_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RIO_MSG_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) rmu->msg_tx_ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) virt_buffer[j],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) rmu->msg_tx_ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) phys_buffer[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* Initialize outbound message descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) rmu->msg_tx_ring.virt = dma_alloc_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) &rmu->msg_tx_ring.phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!rmu->msg_tx_ring.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) goto out_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) rmu->msg_tx_ring.tx_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* Point dequeue/enqueue pointers at first entry in ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) out_be32(&rmu->msg_regs->odqdpar, rmu->msg_tx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) out_be32(&rmu->msg_regs->odqepar, rmu->msg_tx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /* Configure for snooping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) out_be32(&rmu->msg_regs->osar, 0x00000004);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) out_be32(&rmu->msg_regs->osr, 0x000000b3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* Hook up outbound message handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) rc = request_irq(IRQ_RIO_TX(mport), fsl_rio_tx_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "msg_tx", (void *)mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) goto out_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * Configure outbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * Snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * Interrupts (all enabled, except QEIE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * Chaining mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) out_be32(&rmu->msg_regs->omr, 0x00100220);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /* Set number of entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) out_be32(&rmu->msg_regs->omr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) in_be32(&rmu->msg_regs->omr) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ((get_bitmask_order(entries) - 2) << 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /* Now enable the unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) out_be32(&rmu->msg_regs->omr, in_be32(&rmu->msg_regs->omr) | 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) out_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) dma_free_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) out_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) for (i = 0; i < rmu->msg_tx_ring.size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dma_free_coherent(priv->dev, RIO_MSG_BUFFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) rmu->msg_tx_ring.virt_buffer[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) rmu->msg_tx_ring.phys_buffer[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) * fsl_close_outb_mbox - Shut down MPC85xx outbound mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * @mport: Master port implementing the outbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * @mbox: Mailbox to close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Disables the outbound message unit, free all buffers, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * frees the outbound message interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) void fsl_close_outb_mbox(struct rio_mport *mport, int mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /* Disable inbound message unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) out_be32(&rmu->msg_regs->omr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /* Free ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dma_free_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) rmu->msg_tx_ring.size * RIO_MSG_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) rmu->msg_tx_ring.virt, rmu->msg_tx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* Free interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) free_irq(IRQ_RIO_TX(mport), (void *)mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * fsl_open_inb_mbox - Initialize MPC85xx inbound mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * @mport: Master port implementing the inbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * @dev_id: Device specific pointer to pass on event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * @mbox: Mailbox to open
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * @entries: Number of entries in the inbound mailbox ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * Initializes buffer ring, request the inbound message interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * and enables the inbound message unit. Returns %0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * and %-EINVAL or %-ENOMEM on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) fsl_open_inb_mbox(struct rio_mport *mport, void *dev_id, int mbox, int entries)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) int i, rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if ((entries < RIO_MIN_RX_RING_SIZE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) (entries > RIO_MAX_RX_RING_SIZE) || (!is_power_of_2(entries))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* Initialize client buffer ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) rmu->msg_rx_ring.dev_id = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) rmu->msg_rx_ring.size = entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) rmu->msg_rx_ring.rx_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) for (i = 0; i < rmu->msg_rx_ring.size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) rmu->msg_rx_ring.virt_buffer[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* Initialize inbound message ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) rmu->msg_rx_ring.virt = dma_alloc_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) &rmu->msg_rx_ring.phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!rmu->msg_rx_ring.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /* Point dequeue/enqueue pointers at first entry in ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) out_be32(&rmu->msg_regs->ifqdpar, (u32) rmu->msg_rx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) out_be32(&rmu->msg_regs->ifqepar, (u32) rmu->msg_rx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) out_be32(&rmu->msg_regs->isr, 0x00000091);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* Hook up inbound message handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) rc = request_irq(IRQ_RIO_RX(mport), fsl_rio_rx_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) "msg_rx", (void *)mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dma_free_coherent(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * Configure inbound message unit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Snooping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * 4KB max message size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * Unmask all interrupt sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * Disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) out_be32(&rmu->msg_regs->imr, 0x001b0060);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /* Set number of queue entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) setbits32(&rmu->msg_regs->imr, (get_bitmask_order(entries) - 2) << 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Now enable the unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) setbits32(&rmu->msg_regs->imr, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * fsl_close_inb_mbox - Shut down MPC85xx inbound mailbox
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * @mport: Master port implementing the inbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * @mbox: Mailbox to close
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * Disables the inbound message unit, free all buffers, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) * frees the inbound message interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) void fsl_close_inb_mbox(struct rio_mport *mport, int mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Disable inbound message unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) out_be32(&rmu->msg_regs->imr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Free ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dma_free_coherent(priv->dev, rmu->msg_rx_ring.size * RIO_MAX_MSG_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rmu->msg_rx_ring.virt, rmu->msg_rx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) /* Free interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) free_irq(IRQ_RIO_RX(mport), (void *)mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * fsl_add_inb_buffer - Add buffer to the MPC85xx inbound message queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * @mport: Master port implementing the inbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * @mbox: Inbound mailbox number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) * @buf: Buffer to add to inbound queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * Adds the @buf buffer to the MPC85xx inbound message queue. Returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * %0 on success or %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int fsl_add_inb_buffer(struct rio_mport *mport, int mbox, void *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) pr_debug("RIO: fsl_add_inb_buffer(), msg_rx_ring.rx_slot %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) rmu->msg_rx_ring.rx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) "RIO: error adding inbound buffer %d, buffer exists\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) rmu->msg_rx_ring.rx_slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) rmu->msg_rx_ring.virt_buffer[rmu->msg_rx_ring.rx_slot] = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (++rmu->msg_rx_ring.rx_slot == rmu->msg_rx_ring.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) rmu->msg_rx_ring.rx_slot = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * fsl_get_inb_message - Fetch inbound message from the MPC85xx message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * @mport: Master port implementing the inbound message unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * @mbox: Inbound mailbox number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * Gets the next available inbound message from the inbound message queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * A pointer to the message is returned on success or NULL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) void *fsl_get_inb_message(struct rio_mport *mport, int mbox)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct fsl_rmu *rmu = GET_RMM_HANDLE(mport);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) u32 phys_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) void *virt_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) void *buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) phys_buf = in_be32(&rmu->msg_regs->ifqdpar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) /* If no more messages, then bail out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (phys_buf == in_be32(&rmu->msg_regs->ifqepar))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) goto out2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) virt_buf = rmu->msg_rx_ring.virt + (phys_buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) - rmu->msg_rx_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) buf_idx = (phys_buf - rmu->msg_rx_ring.phys) / RIO_MAX_MSG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) buf = rmu->msg_rx_ring.virt_buffer[buf_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (!buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) "RIO: inbound message copy failed, no buffers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* Copy max message size, caller is expected to allocate that big */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) memcpy(buf, virt_buf, RIO_MAX_MSG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) /* Clear the available buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) rmu->msg_rx_ring.virt_buffer[buf_idx] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) setbits32(&rmu->msg_regs->imr, RIO_MSG_IMR_MI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) out2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) * fsl_rio_doorbell_init - MPC85xx doorbell interface init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * @mport: Master port implementing the inbound doorbell unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * Initializes doorbell unit hardware and inbound DMA buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * ring. Called from fsl_rio_setup(). Returns %0 on success
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * or %-ENOMEM on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) int fsl_rio_doorbell_init(struct fsl_rio_dbell *dbell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Initialize inbound doorbells */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dbell->dbell_ring.virt = dma_alloc_coherent(dbell->dev, 512 *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) DOORBELL_MESSAGE_SIZE, &dbell->dbell_ring.phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (!dbell->dbell_ring.virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) printk(KERN_ERR "RIO: unable allocate inbound doorbell ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* Point dequeue/enqueue pointers at first entry in ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) out_be32(&dbell->dbell_regs->dqdpar, (u32) dbell->dbell_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) out_be32(&dbell->dbell_regs->dqepar, (u32) dbell->dbell_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Clear interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) out_be32(&dbell->dbell_regs->dsr, 0x00000091);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Hook up doorbell handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) rc = request_irq(IRQ_RIO_BELL(dbell), fsl_rio_dbell_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "dbell_rx", (void *)dbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dma_free_coherent(dbell->dev, 512 * DOORBELL_MESSAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) dbell->dbell_ring.virt, dbell->dbell_ring.phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "MPC85xx RIO: unable to request inbound doorbell irq");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* Configure doorbells for snooping, 512 entries, and enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) out_be32(&dbell->dbell_regs->dmr, 0x00108161);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) int fsl_rio_setup_rmu(struct rio_mport *mport, struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) struct rio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct fsl_rmu *rmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u64 msg_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) const u32 *msg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) int mlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int aw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (!mport || !mport->priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (!node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) dev_warn(priv->dev, "Can't get %pOF property 'fsl,rmu'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) priv->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) rmu = kzalloc(sizeof(struct fsl_rmu), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (!rmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) aw = of_n_addr_cells(node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) msg_addr = of_get_property(node, "reg", &mlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (!msg_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pr_err("%pOF: unable to find 'reg' property of message-unit\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) kfree(rmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) msg_start = of_read_number(msg_addr, aw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) rmu->msg_regs = (struct rio_msg_regs *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) (rmu_regs_win + (u32)msg_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) rmu->txirq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) rmu->rxirq = irq_of_parse_and_map(node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) printk(KERN_INFO "%pOF: txirq: %d, rxirq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) node, rmu->txirq, rmu->rxirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) priv->rmm_handle = rmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) rio_init_dbell_res(&mport->riores[RIO_DOORBELL_RESOURCE], 0, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) rio_init_mbox_res(&mport->riores[RIO_INB_MBOX_RESOURCE], 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) rio_init_mbox_res(&mport->riores[RIO_OUTB_MBOX_RESOURCE], 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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