Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Freescale MPC85xx/MPC86xx RapidIO support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2009 Sysgo AG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Thomas Moll <thomas.moll@sysgo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * - fixed maintenance access routines, check for aligned access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Copyright 2009 Integrated Device Technology, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Alex Bounine <alexandre.bounine@idt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * - Added Port-Write message handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * - Added Machine Check exception handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Copyright (C) 2007, 2008, 2010, 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Zhang Wei <wei.zhang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * Copyright 2005 MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Matt Porter <mporter@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/extable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include "fsl_rio.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #undef DEBUG_PW	/* Port-Write debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RIO_PORT1_EDCSR		0x0640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RIO_PORT2_EDCSR		0x0680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RIO_PORT1_IECSR		0x10130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RIO_PORT2_IECSR		0x101B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RIO_GCCSR		0x13c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define RIO_ESCSR		0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define ESCSR_CLEAR		0x07120204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define RIO_PORT2_ESCSR		0x178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define RIO_CCSR		0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RIO_LTLEDCSR_IER	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define RIO_LTLEDCSR_PRT	0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define IECSR_CLEAR		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define RIO_ISR_AACR		0x10120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define RIO_ISR_AACR_AA		0x1	/* Accept All ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RIWTAR_TRAD_VAL_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define RIWTAR_TRAD_MASK	0x00FFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RIWBAR_BADD_VAL_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define RIWBAR_BADD_MASK	0x003FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define RIWAR_ENABLE		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define RIWAR_TGINT_LOCAL	0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define RIWAR_RDTYP_NO_SNOOP	0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define RIWAR_RDTYP_SNOOP	0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RIWAR_WRTYP_NO_SNOOP	0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define RIWAR_WRTYP_SNOOP	0x00005000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define RIWAR_WRTYP_ALLOC	0x00006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define RIWAR_SIZE_MASK		0x0000003F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) static DEFINE_SPINLOCK(fsl_rio_config_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define __fsl_read_rio_config(x, addr, err, op)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__asm__ __volatile__(				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		"1:	"op" %1,0(%2)\n"		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		"	eieio\n"			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		"2:\n"					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		".section .fixup,\"ax\"\n"		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		"3:	li %1,-1\n"			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		"	li %0,%3\n"			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		"	b 2b\n"				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		".previous\n"				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		EX_TABLE(1b, 3b)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		: "=r" (err), "=r" (x)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		: "b" (addr), "i" (-EFAULT), "0" (err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) void __iomem *rio_regs_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) void __iomem *rmu_regs_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) resource_size_t rio_law_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) struct fsl_rio_dbell *dbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) struct fsl_rio_pw *pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #ifdef CONFIG_E500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) int fsl_rio_mcheck_exception(struct pt_regs *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	const struct exception_table_entry *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned long reason;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!rio_regs_win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	reason = in_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	if (reason & (RIO_LTLEDCSR_IER | RIO_LTLEDCSR_PRT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		/* Check if we are prepared to handle this fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		entry = search_exception_tables(regs->nip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		if (entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			pr_debug("RIO: %s - MC Exception handled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 				 __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 			out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 				 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			regs->msr |= MSR_RI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			regs->nip = extable_fixup(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EXPORT_SYMBOL_GPL(fsl_rio_mcheck_exception);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * fsl_local_config_read - Generate a MPC85xx local config space read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * @mport: RapidIO master port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * @index: ID of RapdiIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  * @offset: Offset into configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * @len: Length (in bytes) of the maintenance transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  * @data: Value to be read into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * Generates a MPC85xx local configuration space read. Returns %0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  * success or %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int fsl_local_config_read(struct rio_mport *mport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 				int index, u32 offset, int len, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	pr_debug("fsl_local_config_read: index %d offset %8.8x\n", index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	*data = in_be32(priv->regs_win + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * fsl_local_config_write - Generate a MPC85xx local config space write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @mport: RapidIO master port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * @index: ID of RapdiIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * @offset: Offset into configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * @len: Length (in bytes) of the maintenance transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * @data: Value to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  * Generates a MPC85xx local configuration space write. Returns %0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)  * success or %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int fsl_local_config_write(struct rio_mport *mport,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 				int index, u32 offset, int len, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	pr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		("fsl_local_config_write: index %d offset %8.8x data %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		index, offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	out_be32(priv->regs_win + offset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * fsl_rio_config_read - Generate a MPC85xx read maintenance transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * @mport: RapidIO master port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * @index: ID of RapdiIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * @destid: Destination ID of transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * @hopcount: Number of hops to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * @offset: Offset into configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * @len: Length (in bytes) of the maintenance transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * @val: Location to be read into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * Generates a MPC85xx read maintenance transaction. Returns %0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * success or %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) fsl_rio_config_read(struct rio_mport *mport, int index, u16 destid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			u8 hopcount, u32 offset, int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	u32 rval, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	pr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		("fsl_rio_config_read:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		" index %d destid %d hopcount %d offset %8.8x len %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		index, destid, hopcount, offset, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	/* 16MB maintenance window possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* allow only aligned access to maintenance registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	spin_lock_irqsave(&fsl_rio_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	out_be32(&priv->maint_atmu_regs->rowtar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		 (destid << 22) | (hopcount << 12) | (offset >> 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		__fsl_read_rio_config(rval, data, err, "lbz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		__fsl_read_rio_config(rval, data, err, "lhz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		__fsl_read_rio_config(rval, data, err, "lwz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		pr_debug("RIO: cfg_read error %d for %x:%x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 			 err, destid, hopcount, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	*val = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)  * fsl_rio_config_write - Generate a MPC85xx write maintenance transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)  * @mport: RapidIO master port info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)  * @index: ID of RapdiIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)  * @destid: Destination ID of transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)  * @hopcount: Number of hops to target device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)  * @offset: Offset into configuration space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)  * @len: Length (in bytes) of the maintenance transaction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)  * @val: Value to be written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * Generates an MPC85xx write maintenance transaction. Returns %0 on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  * success or %-EINVAL on failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) fsl_rio_config_write(struct rio_mport *mport, int index, u16 destid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 			u8 hopcount, u32 offset, int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	pr_debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		("fsl_rio_config_write:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		" index %d destid %d hopcount %d offset %8.8x len %d val %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		index, destid, hopcount, offset, len, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	/* 16MB maintenance windows possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	/* allow only aligned access to maintenance registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	if (offset > (0x1000000 - len) || !IS_ALIGNED(offset, len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	spin_lock_irqsave(&fsl_rio_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	out_be32(&priv->maint_atmu_regs->rowtar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		 (destid << 22) | (hopcount << 12) | (offset >> 12));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	out_be32(&priv->maint_atmu_regs->rowtear, (destid >> 10));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	data = (u8 *) priv->maint_win + (offset & (RIO_MAINT_WIN_SIZE - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	switch (len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		out_8((u8 *) data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		out_be16((u16 *) data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		out_be32((u32 *) data, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	spin_unlock_irqrestore(&fsl_rio_config_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void fsl_rio_inbound_mem_init(struct rio_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	/* close inbound windows */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		out_be32(&priv->inb_atmu_regs[i].riwar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int fsl_map_inb_mem(struct rio_mport *mport, dma_addr_t lstart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	u64 rstart, u64 size, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	u32 base_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	unsigned int base_size_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	u64 win_start, win_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	u32 riwar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	if ((size & (size - 1)) != 0 || size > 0x400000000ULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	base_size_log = ilog2(size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	base_size = 1 << base_size_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	/* check if addresses are aligned with the window size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	if (lstart & (base_size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	if (rstart & (base_size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	/* check for conflicting ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		if ((riwar & RIWAR_ENABLE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		win_start = ((u64)(in_be32(&priv->inb_atmu_regs[i].riwbar) & RIWBAR_BADD_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			<< RIWBAR_BADD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		win_end = win_start + ((1 << ((riwar & RIWAR_SIZE_MASK) + 1)) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (rstart < win_end && (rstart + size) > win_start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	/* find unused atmu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		if ((riwar & RIWAR_ENABLE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (i >= RIO_INB_ATMU_COUNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	out_be32(&priv->inb_atmu_regs[i].riwtar, lstart >> RIWTAR_TRAD_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	out_be32(&priv->inb_atmu_regs[i].riwbar, rstart >> RIWBAR_BADD_VAL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	out_be32(&priv->inb_atmu_regs[i].riwar, RIWAR_ENABLE | RIWAR_TGINT_LOCAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		RIWAR_RDTYP_SNOOP | RIWAR_WRTYP_SNOOP | (base_size_log - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) void fsl_unmap_inb_mem(struct rio_mport *mport, dma_addr_t lstart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u32 win_start_shift, base_start_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct rio_priv *priv = mport->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u32 riwar, riwtar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* skip default window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	base_start_shift = lstart >> RIWTAR_TRAD_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	for (i = 0; i < RIO_INB_ATMU_COUNT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		riwar = in_be32(&priv->inb_atmu_regs[i].riwar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		if ((riwar & RIWAR_ENABLE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		riwtar = in_be32(&priv->inb_atmu_regs[i].riwtar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		win_start_shift = riwtar & RIWTAR_TRAD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		if (win_start_shift == base_start_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 			out_be32(&priv->inb_atmu_regs[i].riwar, riwar & ~RIWAR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) void fsl_rio_port_error_handler(int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	/*XXX: Error recovery is not implemented, we just clear errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	out_be32((u32 *)(rio_regs_win + RIO_LTLEDCSR), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (offset == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		out_be32((u32 *)(rio_regs_win + RIO_PORT1_EDCSR), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		out_be32((u32 *)(rio_regs_win + RIO_PORT1_IECSR), IECSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		out_be32((u32 *)(rio_regs_win + RIO_ESCSR), ESCSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		out_be32((u32 *)(rio_regs_win + RIO_PORT2_EDCSR), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		out_be32((u32 *)(rio_regs_win + RIO_PORT2_IECSR), IECSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		out_be32((u32 *)(rio_regs_win + RIO_PORT2_ESCSR), ESCSR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline void fsl_rio_info(struct device *dev, u32 ccsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	const char *str;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (ccsr & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		/* Serial phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		switch (ccsr >> 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			str = "1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			str = "4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			str = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		dev_info(dev, "Hardware port width: %s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		switch ((ccsr >> 27) & 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			str = "Single-lane 0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 			str = "Single-lane 2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 			str = "Four-lane";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 			str = "Unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		dev_info(dev, "Training connection status: %s\n", str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		/* Parallel phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		if (!(ccsr & 0x80000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			dev_info(dev, "Output port operating in 8-bit mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		if (!(ccsr & 0x08000000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			dev_info(dev, "Input port operating in 8-bit mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)  * fsl_rio_setup - Setup Freescale PowerPC RapidIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)  * @dev: platform_device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)  * Initializes MPC85xx RapidIO hardware interface, configures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)  * master port with system-specific info, and registers the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)  * master port with the RapidIO subsystem.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int fsl_rio_setup(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	struct rio_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	struct rio_mport *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	struct rio_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	const u32 *dt_range, *cell, *port_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	u32 active_ports = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	struct resource regs, rmu_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	struct device_node *np, *rmu_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	int rlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	u32 ccsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	u64 range_start, range_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	int paw, aw, sw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	static int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	struct device_node *rmu_np[MAX_MSG_UNIT_NUM] = {NULL};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (!dev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		dev_err(&dev->dev, "Device OF-Node is NULL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	rc = of_address_to_resource(dev->dev.of_node, 0, &regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 				dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	dev_info(&dev->dev, "Of-device full name %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	dev_info(&dev->dev, "Regs: %pR\n", &regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	rio_regs_win = ioremap(regs.start, resource_size(&regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	if (!rio_regs_win) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		dev_err(&dev->dev, "Unable to map rio register window\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		goto err_rio_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	ops = kzalloc(sizeof(struct rio_ops), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	if (!ops) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		goto err_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	ops->lcread = fsl_local_config_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	ops->lcwrite = fsl_local_config_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	ops->cread = fsl_rio_config_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	ops->cwrite = fsl_rio_config_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	ops->dsend = fsl_rio_doorbell_send;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	ops->pwenable = fsl_rio_pw_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	ops->open_outb_mbox = fsl_open_outb_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 	ops->open_inb_mbox = fsl_open_inb_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	ops->close_outb_mbox = fsl_close_outb_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	ops->close_inb_mbox = fsl_close_inb_mbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	ops->add_outb_message = fsl_add_outb_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	ops->add_inb_buffer = fsl_add_inb_buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	ops->get_inb_message = fsl_get_inb_message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	ops->map_inb = fsl_map_inb_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	ops->unmap_inb = fsl_unmap_inb_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	rmu_node = of_parse_phandle(dev->dev.of_node, "fsl,srio-rmu-handle", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	if (!rmu_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		dev_err(&dev->dev, "No valid fsl,srio-rmu-handle property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		rc = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		goto err_rmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	rc = of_address_to_resource(rmu_node, 0, &rmu_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		dev_err(&dev->dev, "Can't get %pOF property 'reg'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 				rmu_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		goto err_rmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	rmu_regs_win = ioremap(rmu_regs.start, resource_size(&rmu_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	if (!rmu_regs_win) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		dev_err(&dev->dev, "Unable to map rmu register window\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		goto err_rmu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	for_each_compatible_node(np, NULL, "fsl,srio-msg-unit") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		rmu_np[tmp] = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		tmp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	/*set up doobell node*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	np = of_find_compatible_node(NULL, NULL, "fsl,srio-dbell-unit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		dev_err(&dev->dev, "No fsl,srio-dbell-unit node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		goto err_dbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	dbell = kzalloc(sizeof(struct fsl_rio_dbell), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	if (!(dbell)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_dbell'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		goto err_dbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	dbell->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	dbell->bellirq = irq_of_parse_and_map(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	dev_info(&dev->dev, "bellirq: %d\n", dbell->bellirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	aw = of_n_addr_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	dt_range = of_get_property(np, "reg", &rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	if (!dt_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 		pr_err("%pOF: unable to find 'reg' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 			np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 		goto err_pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	range_start = of_read_number(dt_range, aw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	dbell->dbell_regs = (struct rio_dbell_regs *)(rmu_regs_win +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 				(u32)range_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	/*set up port write node*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	np = of_find_compatible_node(NULL, NULL, "fsl,srio-port-write-unit");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		dev_err(&dev->dev, "No fsl,srio-port-write-unit node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 		goto err_pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	pw = kzalloc(sizeof(struct fsl_rio_pw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	if (!(pw)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		dev_err(&dev->dev, "Can't alloc memory for 'fsl_rio_pw'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		goto err_pw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	pw->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	pw->pwirq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	dev_info(&dev->dev, "pwirq: %d\n", pw->pwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	aw = of_n_addr_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	dt_range = of_get_property(np, "reg", &rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	if (!dt_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		pr_err("%pOF: unable to find 'reg' property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 			np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 		rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	range_start = of_read_number(dt_range, aw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	pw->pw_regs = (struct rio_pw_regs *)(rmu_regs_win + (u32)range_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	/*set up ports node*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	for_each_child_of_node(dev->dev.of_node, np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 		port_index = of_get_property(np, "cell-index", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 		if (!port_index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 			dev_err(&dev->dev, "Can't get %pOF property 'cell-index'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 					np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		dt_range = of_get_property(np, "ranges", &rlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		if (!dt_range) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 			dev_err(&dev->dev, "Can't get %pOF property 'ranges'\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 					np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 		/* Get node address wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 		cell = of_get_property(np, "#address-cells", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		if (cell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 			aw = *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 			aw = of_n_addr_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 		/* Get node size wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 		cell = of_get_property(np, "#size-cells", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		if (cell)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 			sw = *cell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 			sw = of_n_size_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 		/* Get parent address wide wide */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 		paw = of_n_addr_cells(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 		range_start = of_read_number(dt_range + aw, paw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 		range_size = of_read_number(dt_range + aw + paw, sw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		dev_info(&dev->dev, "%pOF: LAW start 0x%016llx, size 0x%016llx.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 				np, range_start, range_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		port = kzalloc(sizeof(struct rio_mport), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 		if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 		rc = rio_mport_initialize(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 		if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 			kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 		i = *port_index - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 		port->index = (unsigned char)i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 		priv = kzalloc(sizeof(struct rio_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 		if (!priv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 			dev_err(&dev->dev, "Can't alloc memory for 'priv'\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) 			kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 		INIT_LIST_HEAD(&port->dbells);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 		port->iores.start = range_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 		port->iores.end = port->iores.start + range_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 		port->iores.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) 		port->iores.name = "rio_io_win";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) 		if (request_resource(&iomem_resource, &port->iores) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) 			dev_err(&dev->dev, "RIO: Error requesting master port region"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 				" 0x%016llx-0x%016llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 				(u64)port->iores.start, (u64)port->iores.end);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 				kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 				kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) 		sprintf(port->name, "RIO mport %d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) 		priv->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 		port->dev.parent = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) 		port->ops = ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 		port->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 		port->phys_efptr = 0x100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 		port->phys_rmap = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 		priv->regs_win = rio_regs_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 		ccsr = in_be32(priv->regs_win + RIO_CCSR + i*0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 		/* Checking the port training status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) 		if (in_be32((priv->regs_win + RIO_ESCSR + i*0x20)) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 			dev_err(&dev->dev, "Port %d is not ready. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) 			"Try to restart connection...\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 			/* Disable ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) 			out_be32(priv->regs_win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 				+ RIO_CCSR + i*0x20, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) 			/* Set 1x lane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) 			setbits32(priv->regs_win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 				+ RIO_CCSR + i*0x20, 0x02000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) 			/* Enable ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) 			setbits32(priv->regs_win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 				+ RIO_CCSR + i*0x20, 0x00600000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 			msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) 			if (in_be32((priv->regs_win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 					+ RIO_ESCSR + i*0x20)) & 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) 				dev_err(&dev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) 					"Port %d restart failed.\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) 				release_resource(&port->iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) 				kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) 				kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) 			dev_info(&dev->dev, "Port %d restart success!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 		fsl_rio_info(&dev->dev, ccsr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) 		port->sys_size = (in_be32((priv->regs_win + RIO_PEF_CAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) 					& RIO_PEF_CTLS) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) 		dev_info(&dev->dev, "RapidIO Common Transport System size: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) 				port->sys_size ? 65536 : 256);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) 		if (port->host_deviceid >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) 			out_be32(priv->regs_win + RIO_GCCSR, RIO_PORT_GEN_HOST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) 				RIO_PORT_GEN_MASTER | RIO_PORT_GEN_DISCOVERED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) 			out_be32(priv->regs_win + RIO_GCCSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) 				RIO_PORT_GEN_MASTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) 		priv->atmu_regs = (struct rio_atmu_regs *)(priv->regs_win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) 			+ ((i == 0) ? RIO_ATMU_REGS_PORT1_OFFSET :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) 			RIO_ATMU_REGS_PORT2_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) 		priv->maint_atmu_regs = priv->atmu_regs + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) 		priv->inb_atmu_regs = (struct rio_inb_atmu_regs __iomem *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) 			(priv->regs_win +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) 			((i == 0) ? RIO_INB_ATMU_REGS_PORT1_OFFSET :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) 			RIO_INB_ATMU_REGS_PORT2_OFFSET));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) 		/* Set to receive packets with any dest ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) 		out_be32((priv->regs_win + RIO_ISR_AACR + i*0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) 			 RIO_ISR_AACR_AA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) 		/* Configure maintenance transaction window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) 		out_be32(&priv->maint_atmu_regs->rowbar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) 			port->iores.start >> 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) 		out_be32(&priv->maint_atmu_regs->rowar,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) 			 0x80077000 | (ilog2(RIO_MAINT_WIN_SIZE) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) 		priv->maint_win = ioremap(port->iores.start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 				RIO_MAINT_WIN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) 		rio_law_start = range_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) 		fsl_rio_setup_rmu(port, rmu_np[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) 		fsl_rio_inbound_mem_init(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) 		dbell->mport[i] = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) 		pw->mport[i] = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) 		if (rio_register_mport(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) 			release_resource(&port->iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) 			kfree(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) 			kfree(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) 			continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) 		active_ports++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) 	if (!active_ports) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 		rc = -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) 	fsl_rio_doorbell_init(dbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) 	fsl_rio_port_write_init(pw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) 	kfree(pw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) 	pw = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) err_pw:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) 	kfree(dbell);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) 	dbell = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) err_dbell:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) 	iounmap(rmu_regs_win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) 	rmu_regs_win = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) err_rmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) 	kfree(ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) err_ops:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) 	iounmap(rio_regs_win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) 	rio_regs_win = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) err_rio_regs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 	return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* The probe function for RapidIO peer-to-peer network.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int fsl_of_rio_rpn_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) 	printk(KERN_INFO "Setting up RapidIO peer-to-peer network %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 			dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) 	return fsl_rio_setup(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct of_device_id fsl_of_rio_rpn_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 		.compatible = "fsl,srio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static struct platform_driver fsl_of_rio_rpn_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) 		.name = "fsl-of-rio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) 		.of_match_table = fsl_of_rio_rpn_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) 	.probe = fsl_of_rio_rpn_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static __init int fsl_of_rio_rpn_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 	return platform_driver_register(&fsl_of_rio_rpn_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) subsys_initcall(fsl_of_rio_rpn_init);