^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * MPC85xx/86xx PCI Express structure define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2007,2011 Freescale Semiconductor, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifdef __KERNEL__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __POWERPC_FSL_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __POWERPC_FSL_PCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) struct platform_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* FSL PCI controller BRR1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PCI_FSL_BRR1 0xbf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PCI_FSL_BRR1_VER 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PCIE_LTSSM_L0 0x16 /* L0 state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PIWAR_EN 0x80000000 /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PIWAR_PF 0x20000000 /* prefetch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PIWAR_READ_SNOOP 0x00050000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PIWAR_WRITE_SNOOP 0x00005000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PIWAR_SZ_MASK 0x0000003f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PEX_PMCR_PTOMR 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PEX_PMCR_EXL2S 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PME_DISR_EN_PTOD 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PME_DISR_EN_ENL23D 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PME_DISR_EN_EXL23D 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* PCI/PCI Express outbound window reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct pci_outbound_window_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) __be32 potar; /* 0x.0 - Outbound translation address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __be32 potear; /* 0x.4 - Outbound translation extended address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) __be32 powbar; /* 0x.8 - Outbound window base address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u8 res1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) __be32 powar; /* 0x.10 - Outbound window attributes register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u8 res2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* PCI/PCI Express inbound window reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct pci_inbound_window_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) __be32 pitar; /* 0x.0 - Inbound translation address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u8 res1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) __be32 piwbar; /* 0x.8 - Inbound window base address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) __be32 piwbear; /* 0x.c - Inbound window base extended address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) __be32 piwar; /* 0x.10 - Inbound window attributes register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u8 res2[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* PCI/PCI Express IO block registers for 85xx/86xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct ccsr_pci {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) __be32 config_addr; /* 0x.000 - PCI/PCIE Configuration Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) __be32 config_data; /* 0x.004 - PCI/PCIE Configuration Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 res2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) __be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u8 res3[3016];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) __be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) __be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PCI/PCI Express outbound window 0-4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Window 0 is the default window and is the only window enabled upon reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * The default outbound register set is used when a transaction misses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * in all of the other outbound windows.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct pci_outbound_window_regs pow[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u8 res14[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u8 res6[96];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* PCI/PCI Express inbound window 3-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * inbound window 1 supports only a 32-bit base address and does not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * define an inbound window base extended address register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct pci_inbound_window_regs piw[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 res21[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) __be32 pex_err_en; /* 0x.e08 - PCI/PCIE error interrupt enable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 res22[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) __be32 pex_err_disr; /* 0x.e10 - PCI/PCIE error disable register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 res23[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) __be32 pex_err_cap_stat; /* 0x.e20 - PCI/PCIE error capture status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 res24[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) __be32 pex_err_cap_r0; /* 0x.e28 - PCIE error capture register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) __be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) __be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) __be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u8 res_e38[200];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) __be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u8 res_f04[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define PEX_CSR0_LTSSM_MASK 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PEX_CSR0_LTSSM_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PEX_CSR0_LTSSM_L0 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) __be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 res_f1c[228];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) extern void fsl_pcibios_fixup_bus(struct pci_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) extern void fsl_pcibios_fixup_phb(struct pci_controller *phb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern int mpc83xx_add_bridge(struct device_node *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u64 fsl_pci_immrbar_base(struct pci_controller *hose);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern struct device_node *fsl_pci_primary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) void fsl_pci_assign_primary(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static inline void fsl_pci_assign_primary(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #ifdef CONFIG_FSL_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) extern int fsl_pci_mcheck_exception(struct pt_regs *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static inline int fsl_pci_mcheck_exception(struct pt_regs *regs) {return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #endif /* __POWERPC_FSL_PCI_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #endif /* __KERNEL__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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