Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Author: Tony Li <tony.li@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *	   Jason Jin <Jason.jin@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _POWERPC_SYSDEV_FSL_MSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _POWERPC_SYSDEV_FSL_MSI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/msi_bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define NR_MSI_REG_MSIIR	8  /* MSIIR can index 8 MSI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NR_MSI_REG_MSIIR1	16 /* MSIIR1 can index 16 MSI registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define NR_MSI_REG_MAX		NR_MSI_REG_MSIIR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IRQS_PER_MSI_REG	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NR_MSI_IRQS_MAX	(NR_MSI_REG_MAX * IRQS_PER_MSI_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FSL_PIC_IP_MASK   0x0000000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define FSL_PIC_IP_MPIC   0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FSL_PIC_IP_IPIC   0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FSL_PIC_IP_VMPIC  0x00000003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MSI_HW_ERRATA_ENDIAN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct fsl_msi_cascade_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct fsl_msi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	struct irq_domain *irqhost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	unsigned long cascade_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	u32 msiir_offset; /* Offset of MSIIR, relative to start of CCSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	u32 ibs_shift; /* Shift of interrupt bit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	u32 srs_shift; /* Shift of the shared interrupt register select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	void __iomem *msi_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	u32 feature;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	struct fsl_msi_cascade_data *cascade_array[NR_MSI_REG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	struct msi_bitmap bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	struct list_head list;          /* support multiple MSI banks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	phandle phandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* _POWERPC_SYSDEV_FSL_MSI_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)