^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Tony Li <tony.li@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Jason Jin <Jason.jin@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <sysdev/fsl_soc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/hw_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/ppc-pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mpic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/fsl_hcalls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include "fsl_msi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "fsl_pci.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MSIIR_OFFSET_MASK 0xfffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MSIIR_IBS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MSIIR_SRS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MSIIR1_IBS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MSIIR1_SRS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MSI_SRS_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MSI_IBS_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define msi_hwirq(msi, msir_index, intr_index) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ((msir_index) << (msi)->srs_shift | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ((intr_index) << (msi)->ibs_shift))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static LIST_HEAD(msi_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct fsl_msi_feature {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) u32 fsl_pic_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct fsl_msi_cascade_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct fsl_msi *msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return in_be32(base + (reg >> 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * We do not need this actually. The MSIR register has been read once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * in the cascade interrupt. So, this MSI interrupt has been acked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static void fsl_msi_end_irq(struct irq_data *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct fsl_msi *msi_data = irqd->domain->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int cascade_virq, srs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) cascade_virq = msi_data->cascade_array[srs]->virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) seq_printf(p, " fsl-msi-%d", cascade_virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static struct irq_chip fsl_msi_chip = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .irq_mask = pci_msi_mask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .irq_unmask = pci_msi_unmask_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .irq_ack = fsl_msi_end_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .irq_print_chip = fsl_msi_print_chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) irq_hw_number_t hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct fsl_msi *msi_data = h->host_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct irq_chip *chip = &fsl_msi_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) irq_set_chip_data(virq, msi_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) irq_set_chip_and_handler(virq, chip, handle_edge_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const struct irq_domain_ops fsl_msi_host_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .map = fsl_msi_host_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int rc, hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) irq_domain_get_of_node(msi_data->irqhost));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Reserve all the hwirqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * The available hwirqs will be released in fsl_msi_setup_hwirq()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct fsl_msi *msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) irq_hw_number_t hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) for_each_pci_msi_entry(entry, pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!entry->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) hwirq = virq_to_hw(entry->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msi_data = irq_get_chip_data(entry->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) irq_set_msi_desc(entry->irq, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) irq_dispose_mapping(entry->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct msi_msg *msg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct fsl_msi *fsl_msi_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct fsl_msi *msi_data = fsl_msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pci_controller *hose = pci_bus_to_host(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u64 address; /* Physical address of the MSIIR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const __be64 *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* If the msi-address-64 property exists, then use it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg = of_get_property(hose->dn, "msi-address-64", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (reg && (len == sizeof(u64)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) address = be64_to_cpup(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msg->address_lo = lower_32_bits(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) msg->address_hi = upper_32_bits(address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * MPIC version 2.0 has erratum PIC1. It causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * that neither MSI nor MSI-X can work fine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * This is a workaround to allow MSI-X to function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * properly. It only works for MSI-X, we prevent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * MSI on buggy chips in fsl_setup_msi_irqs().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) msg->data = __swab32(hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) msg->data = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct pci_controller *hose = pci_bus_to_host(pdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) phandle phandle = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int rc, hwirq = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct msi_desc *entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct msi_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct fsl_msi *msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (type == PCI_CAP_ID_MSI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * MPIC version 2.0 has erratum PIC1. For now MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * could not work. So check to prevent MSI from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * being used on the board with this erratum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) list_for_each_entry(msi_data, &msi_head, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * If the PCI node has an fsl,msi property, then we need to use it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * to find the specific MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) np = of_parse_phandle(hose->dn, "fsl,msi", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (of_device_is_compatible(np, "fsl,mpic-msi") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) of_device_is_compatible(np, "fsl,vmpic-msi") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) phandle = np->phandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "node %pOF has an invalid fsl,msi phandle %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hose->dn, np->phandle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) for_each_pci_msi_entry(entry, pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Loop over all the MSI devices until we find one that has an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * available interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) list_for_each_entry(msi_data, &msi_head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * If the PCI node has an fsl,msi property, then we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * restrict our search to the corresponding MSI node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * The simplest way is to skip over MSI nodes with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * wrong phandle. Under the Freescale hypervisor, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * has the additional benefit of skipping over MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * nodes that are not mapped in the PAMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (phandle && (phandle != msi_data->phandle))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (hwirq >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (hwirq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rc = hwirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) virq = irq_create_mapping(msi_data->irqhost, hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!virq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) rc = -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) goto out_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* chip_data is msi_data via host->hostdata in host->map() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) irq_set_msi_desc(virq, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pci_write_msi_msg(virq, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) out_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* free by the caller of this function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static irqreturn_t fsl_msi_cascade(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned int cascade_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct fsl_msi *msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int msir_index = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 msir_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 intr_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 have_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct fsl_msi_cascade_data *cascade_data = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) irqreturn_t ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) msi_data = cascade_data->msi_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) msir_index = cascade_data->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (msir_index >= NR_MSI_REG_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cascade_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) switch (msi_data->feature & FSL_PIC_IP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case FSL_PIC_IP_MPIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) msir_value = fsl_msi_read(msi_data->msi_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) msir_index * 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case FSL_PIC_IP_IPIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #ifdef CONFIG_EPAPR_PARAVIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) case FSL_PIC_IP_VMPIC: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "irq %u (ret=%u)\n", irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) msir_value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) while (msir_value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) intr_index = ffs(msir_value) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) cascade_irq = irq_linear_revmap(msi_data->irqhost,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) msi_hwirq(msi_data, msir_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) intr_index + have_shift));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (cascade_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) generic_handle_irq(cascade_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) have_shift += intr_index + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) msir_value = msir_value >> (intr_index + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int fsl_of_msi_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct fsl_msi *msi = platform_get_drvdata(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) int virq, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (msi->list.prev != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) list_del(&msi->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for (i = 0; i < NR_MSI_REG_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (msi->cascade_array[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) virq = msi->cascade_array[i]->virq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) BUG_ON(!virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) free_irq(virq, msi->cascade_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) kfree(msi->cascade_array[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) irq_dispose_mapping(virq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (msi->bitmap.bitmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) msi_bitmap_free(&msi->bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) iounmap(msi->msi_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) kfree(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static struct lock_class_key fsl_msi_irq_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static struct lock_class_key fsl_msi_irq_request_class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int offset, int irq_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct fsl_msi_cascade_data *cascade_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int virt_msir, i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (!virt_msir) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __func__, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!cascade_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_err(&dev->dev, "No memory for MSI cascade data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) &fsl_msi_irq_request_class);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) cascade_data->index = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) cascade_data->msi_data = msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) cascade_data->virq = virt_msir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) msi->cascade_array[irq_index] = cascade_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "fsl-msi-cascade", cascade_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) virt_msir, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Release the hwirqs corresponding to this MSI register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (i = 0; i < IRQS_PER_MSI_REG; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) msi_bitmap_free_hwirqs(&msi->bitmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) msi_hwirq(msi, offset, i), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct of_device_id fsl_of_msi_ids[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int fsl_of_msi_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct fsl_msi *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct resource res, msiir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int err, i, j, irq_index, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) const u32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) const struct fsl_msi_feature *features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct pci_controller *phb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) match = of_match_device(fsl_of_msi_ids, &dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) features = match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) printk(KERN_DEBUG "Setting up Freescale MSI support\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!msi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(&dev->dev, "No memory for MSI structure\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) platform_set_drvdata(dev, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (msi->irqhost == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dev_err(&dev->dev, "No memory for MSI irqhost\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * property. Instead, we use hypercalls to access the MSI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) err = of_address_to_resource(dev->dev.of_node, 0, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev_err(&dev->dev, "invalid resource for node %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) msi->msi_regs = ioremap(res.start, resource_size(&res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!msi->msi_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&dev->dev, "could not map node %pOF\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) msi->msiir_offset =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) features->msiir_offset + (res.start & 0xfffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * First read the MSIIR/MSIIR1 offset from dts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * On failure use the hardcode MSIIR offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) msi->msiir_offset = features->msiir_offset +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) (res.start & MSIIR_OFFSET_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) msi->feature = features->fsl_pic_ip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* For erratum PIC1 on MPIC version 2.0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) && (fsl_mpic_primary_get_version() == 0x0200))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msi->feature |= MSI_HW_ERRATA_ENDIAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * Remember the phandle, so that we can match with any PCI nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * that have an "fsl,msi" property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msi->phandle = dev->dev.of_node->phandle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) err = fsl_msi_init_allocator(msi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dev_err(&dev->dev, "Error allocating MSI bitmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) msi->srs_shift = MSIIR1_SRS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) msi->ibs_shift = MSIIR1_IBS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) irq_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) err = fsl_msi_setup_hwirq(msi, dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) irq_index, irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static const u32 all_avail[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) msi->srs_shift = MSIIR_SRS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msi->ibs_shift = MSIIR_IBS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (p && len % (2 * sizeof(u32)) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!p) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) p = all_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) len = sizeof(all_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (p[i * 2] % IRQS_PER_MSI_REG ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) p[i * 2 + 1] % IRQS_PER_MSI_REG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) pr_warn("%s: %pOF: msi available range of %u at %u is not IRQ-aligned\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) __func__, dev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) p[i * 2 + 1], p[i * 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) offset = p[i * 2] / IRQS_PER_MSI_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) for (j = 0; j < count; j++, irq_index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) err = fsl_msi_setup_hwirq(msi, dev, offset + j,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) irq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) list_add_tail(&msi->list, &msi_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * Apply the MSI ops to all the controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * It doesn't hurt to reassign the same ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * but bail out if we find another MSI driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) list_for_each_entry(phb, &hose_list, list_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!phb->controller_ops.setup_msi_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) phb->controller_ops.setup_msi_irqs = fsl_setup_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) phb->controller_ops.teardown_msi_irqs = fsl_teardown_msi_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) } else if (phb->controller_ops.setup_msi_irqs != fsl_setup_msi_irqs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) dev_err(&dev->dev, "Different MSI driver already installed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) goto error_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) error_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fsl_of_msi_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct fsl_msi_feature mpic_msi_feature = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .fsl_pic_ip = FSL_PIC_IP_MPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .msiir_offset = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct fsl_msi_feature ipic_msi_feature = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .fsl_pic_ip = FSL_PIC_IP_IPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .msiir_offset = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct fsl_msi_feature vmpic_msi_feature = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .fsl_pic_ip = FSL_PIC_IP_VMPIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .msiir_offset = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static const struct of_device_id fsl_of_msi_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .compatible = "fsl,mpic-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .data = &mpic_msi_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .compatible = "fsl,mpic-msi-v4.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .data = &mpic_msi_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .compatible = "fsl,ipic-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .data = &ipic_msi_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #ifdef CONFIG_EPAPR_PARAVIRT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .compatible = "fsl,vmpic-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .data = &vmpic_msi_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .compatible = "fsl,vmpic-msi-v4.3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .data = &vmpic_msi_feature,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static struct platform_driver fsl_of_msi_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .name = "fsl-msi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .of_match_table = fsl_of_msi_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .probe = fsl_of_msi_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .remove = fsl_of_msi_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static __init int fsl_of_msi_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return platform_driver_register(&fsl_of_msi_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) subsys_initcall(fsl_of_msi_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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