Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Freescale LBC and UPM routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright © 2007-2008  MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright © 2010 Freescale Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Jack Lan <Jack.Lan@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Author: Roy Zang <tie-fei.zang@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/syscore_ops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <asm/fsl_lbc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static DEFINE_SPINLOCK(fsl_lbc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) struct fsl_lbc_ctrl *fsl_lbc_ctrl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) EXPORT_SYMBOL(fsl_lbc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * fsl_lbc_addr - convert the base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * @addr_base:	base address of the memory bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * This function converts a base address of lbc into the right format for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * BR register. If the SOC has eLBC then it returns 32bit physical address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * else it convers a 34bit local bus physical address to correct format of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  * 32bit address for BR register (Example: MPC8641).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) u32 fsl_lbc_addr(phys_addr_t addr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct device_node *np = fsl_lbc_ctrl_dev->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u32 addr = addr_base & 0xffff8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (of_device_is_compatible(np, "fsl,elbc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	return addr | ((addr_base & 0x300000000ull) >> 19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) EXPORT_SYMBOL(fsl_lbc_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * fsl_lbc_find - find Localbus bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @addr_base:	base address of the memory bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * This function walks LBC banks comparing "Base address" field of the BR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * registers with the supplied addr_base argument. When bases match this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * function returns bank number (starting with 0), otherwise it returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  * appropriate errno value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) int fsl_lbc_find(phys_addr_t addr_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct fsl_lbc_regs __iomem *lbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	lbc = fsl_lbc_ctrl_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	for (i = 0; i < ARRAY_SIZE(lbc->bank); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		u32 br = in_be32(&lbc->bank[i].br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		u32 or = in_be32(&lbc->bank[i].or);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		if (br & BR_V && (br & or & BR_BA) == fsl_lbc_addr(addr_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) EXPORT_SYMBOL(fsl_lbc_find);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  * fsl_upm_find - find pre-programmed UPM via base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * @addr_base:	base address of the memory bank controlled by the UPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  * @upm:	pointer to the allocated fsl_upm structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  * This function fills fsl_upm structure so you can use it with the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  * UPM API. On success this function returns 0, otherwise it returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  * appropriate errno value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) int fsl_upm_find(phys_addr_t addr_base, struct fsl_upm *upm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 br;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct fsl_lbc_regs __iomem *lbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	bank = fsl_lbc_find(addr_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (bank < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return bank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	lbc = fsl_lbc_ctrl_dev->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	br = in_be32(&lbc->bank[bank].br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	switch (br & BR_MSEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	case BR_MS_UPMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		upm->mxmr = &lbc->mamr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	case BR_MS_UPMB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		upm->mxmr = &lbc->mbmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	case BR_MS_UPMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		upm->mxmr = &lbc->mcmr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	switch (br & BR_PS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case BR_PS_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		upm->width = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case BR_PS_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		upm->width = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	case BR_PS_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		upm->width = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) EXPORT_SYMBOL(fsl_upm_find);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)  * fsl_upm_run_pattern - actually run an UPM pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)  * @upm:	pointer to the fsl_upm structure obtained via fsl_upm_find
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)  * @io_base:	remapped pointer to where memory access should happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)  * @mar:	MAR register content during pattern execution
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * This function triggers dummy write to the memory specified by the io_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * thus UPM pattern actually executed. Note that mar usage depends on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * pre-programmed AMX bits in the UPM RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) int fsl_upm_run_pattern(struct fsl_upm *upm, void __iomem *io_base, u32 mar)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	spin_lock_irqsave(&fsl_lbc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	out_be32(&fsl_lbc_ctrl_dev->regs->mar, mar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	switch (upm->width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		out_8(io_base, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		out_be16(io_base, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		out_be32(io_base, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	spin_unlock_irqrestore(&fsl_lbc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) EXPORT_SYMBOL(fsl_upm_run_pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static int fsl_lbc_ctrl_init(struct fsl_lbc_ctrl *ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			     struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	/* clear event registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	setbits32(&lbc->ltesr, LTESR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	out_be32(&lbc->lteatr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	out_be32(&lbc->ltear, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	out_be32(&lbc->lteccr, LTECCR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	out_be32(&lbc->ltedr, LTEDR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	/* Set the monitor timeout value to the maximum for erratum A001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	if (of_device_is_compatible(node, "fsl,elbc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		clrsetbits_be32(&lbc->lbcr, LBCR_BMT, LBCR_BMTPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * NOTE: This interrupt is used to report localbus events of various kinds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * such as transaction errors on the chipselects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static irqreturn_t fsl_lbc_ctrl_irq(int irqno, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct fsl_lbc_ctrl *ctrl = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	spin_lock_irqsave(&fsl_lbc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	status = in_be32(&lbc->ltesr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		spin_unlock_irqrestore(&fsl_lbc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	out_be32(&lbc->ltesr, LTESR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	out_be32(&lbc->lteatr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	out_be32(&lbc->ltear, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	ctrl->irq_status = status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	if (status & LTESR_BM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		dev_err(ctrl->dev, "Local bus monitor time-out: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (status & LTESR_WP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		dev_err(ctrl->dev, "Write protect error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (status & LTESR_ATMW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		dev_err(ctrl->dev, "Atomic write error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	if (status & LTESR_ATMR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		dev_err(ctrl->dev, "Atomic read error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	if (status & LTESR_CS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		dev_err(ctrl->dev, "Chip select error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (status & LTESR_FCT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		dev_err(ctrl->dev, "FCM command time-out: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		wake_up(&ctrl->irq_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (status & LTESR_PAR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		dev_err(ctrl->dev, "Parity or Uncorrectable ECC error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		wake_up(&ctrl->irq_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (status & LTESR_CC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		wake_up(&ctrl->irq_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	if (status & ~LTESR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		dev_err(ctrl->dev, "Unknown error: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			"LTESR 0x%08X\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	spin_unlock_irqrestore(&fsl_lbc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * fsl_lbc_ctrl_probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * called by device layer when it finds a device matching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * one our driver can handled. This code allocates all of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * the resources needed for the controller only.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * resources for the NAND banks themselves are allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * in the chip probe function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int fsl_lbc_ctrl_probe(struct platform_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	if (!dev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		dev_err(&dev->dev, "Device OF-Node is NULL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	fsl_lbc_ctrl_dev = kzalloc(sizeof(*fsl_lbc_ctrl_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	if (!fsl_lbc_ctrl_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	dev_set_drvdata(&dev->dev, fsl_lbc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	spin_lock_init(&fsl_lbc_ctrl_dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	init_waitqueue_head(&fsl_lbc_ctrl_dev->irq_wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	fsl_lbc_ctrl_dev->regs = of_iomap(dev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (!fsl_lbc_ctrl_dev->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		dev_err(&dev->dev, "failed to get memory region\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	fsl_lbc_ctrl_dev->irq[0] = irq_of_parse_and_map(dev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	if (!fsl_lbc_ctrl_dev->irq[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		dev_err(&dev->dev, "failed to get irq resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	fsl_lbc_ctrl_dev->dev = &dev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	ret = fsl_lbc_ctrl_init(fsl_lbc_ctrl_dev, dev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	ret = request_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 				"fsl-lbc", fsl_lbc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		dev_err(&dev->dev, "failed to install irq (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			fsl_lbc_ctrl_dev->irq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ret = fsl_lbc_ctrl_dev->irq[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	fsl_lbc_ctrl_dev->irq[1] = irq_of_parse_and_map(dev->dev.of_node, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (fsl_lbc_ctrl_dev->irq[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		ret = request_irq(fsl_lbc_ctrl_dev->irq[1], fsl_lbc_ctrl_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 				IRQF_SHARED, "fsl-lbc-err", fsl_lbc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 			dev_err(&dev->dev, "failed to install irq (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 					fsl_lbc_ctrl_dev->irq[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			ret = fsl_lbc_ctrl_dev->irq[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 			goto err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	/* Enable interrupts for any detected events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	out_be32(&fsl_lbc_ctrl_dev->regs->lteir, LTEIR_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	free_irq(fsl_lbc_ctrl_dev->irq[0], fsl_lbc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	iounmap(fsl_lbc_ctrl_dev->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	kfree(fsl_lbc_ctrl_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	fsl_lbc_ctrl_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* save lbc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int fsl_lbc_syscore_suspend(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	struct fsl_lbc_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	struct fsl_lbc_regs __iomem *lbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	ctrl = fsl_lbc_ctrl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	lbc = ctrl->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (!lbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ctrl->saved_regs = kmalloc(sizeof(struct fsl_lbc_regs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (!ctrl->saved_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	_memcpy_fromio(ctrl->saved_regs, lbc, sizeof(struct fsl_lbc_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* restore lbc registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static void fsl_lbc_syscore_resume(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct fsl_lbc_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	struct fsl_lbc_regs __iomem *lbc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	ctrl = fsl_lbc_ctrl_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (!ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	lbc = ctrl->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	if (!lbc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (ctrl->saved_regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		_memcpy_toio(lbc, ctrl->saved_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 				sizeof(struct fsl_lbc_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		kfree(ctrl->saved_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		ctrl->saved_regs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #endif /* CONFIG_SUSPEND */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const struct of_device_id fsl_lbc_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	{ .compatible = "fsl,elbc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	{ .compatible = "fsl,pq3-localbus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{ .compatible = "fsl,pq2-localbus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	{ .compatible = "fsl,pq2pro-localbus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static struct syscore_ops lbc_syscore_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.suspend = fsl_lbc_syscore_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.resume = fsl_lbc_syscore_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static struct platform_driver fsl_lbc_ctrl_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.name = "fsl-lbc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.of_match_table = fsl_lbc_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	.probe = fsl_lbc_ctrl_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int __init fsl_lbc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #ifdef CONFIG_SUSPEND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	register_syscore_ops(&lbc_syscore_pm_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	return platform_driver_register(&fsl_lbc_ctrl_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) subsys_initcall(fsl_lbc_init);