Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * (c) Copyright 2006 Benjamin Herrenschmidt, IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *                    <benh@kernel.crashing.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #undef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/dcr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #ifdef CONFIG_PPC_DCR_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) static struct device_node *find_dcr_parent(struct device_node *node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	struct device_node *par, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	const u32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	for (par = of_node_get(node); par;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 		if (of_get_property(par, "dcr-controller", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 		p = of_get_property(par, "dcr-parent", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 		tmp = par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 		if (p == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			par = of_get_parent(par);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			par = of_find_node_by_phandle(*p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 		of_node_put(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	return par;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #if defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) bool dcr_map_ok_generic(dcr_host_t host)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	if (host.type == DCR_HOST_NATIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		return dcr_map_ok_native(host.host.native);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	else if (host.type == DCR_HOST_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 		return dcr_map_ok_mmio(host.host.mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) EXPORT_SYMBOL_GPL(dcr_map_ok_generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) dcr_host_t dcr_map_generic(struct device_node *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 			   unsigned int dcr_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 			   unsigned int dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	dcr_host_t host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	const char *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	host.type = DCR_HOST_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	dp = find_dcr_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (dp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		return host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	prop = of_get_property(dp, "dcr-access-method", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	pr_debug("dcr_map_generic(dcr-access-method = %s)\n", prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	if (!strcmp(prop, "native")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		host.type = DCR_HOST_NATIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		host.host.native = dcr_map_native(dev, dcr_n, dcr_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	} else if (!strcmp(prop, "mmio")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		host.type = DCR_HOST_MMIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		host.host.mmio = dcr_map_mmio(dev, dcr_n, dcr_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	of_node_put(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) EXPORT_SYMBOL_GPL(dcr_map_generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) void dcr_unmap_generic(dcr_host_t host, unsigned int dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (host.type == DCR_HOST_NATIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		dcr_unmap_native(host.host.native, dcr_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	else if (host.type == DCR_HOST_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		dcr_unmap_mmio(host.host.mmio, dcr_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	else /* host.type == DCR_HOST_INVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		WARN_ON(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) EXPORT_SYMBOL_GPL(dcr_unmap_generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) u32 dcr_read_generic(dcr_host_t host, unsigned int dcr_n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (host.type == DCR_HOST_NATIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		return dcr_read_native(host.host.native, dcr_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	else if (host.type == DCR_HOST_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		return dcr_read_mmio(host.host.mmio, dcr_n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	else /* host.type == DCR_HOST_INVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		WARN_ON(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) EXPORT_SYMBOL_GPL(dcr_read_generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) void dcr_write_generic(dcr_host_t host, unsigned int dcr_n, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (host.type == DCR_HOST_NATIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		dcr_write_native(host.host.native, dcr_n, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	else if (host.type == DCR_HOST_MMIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		dcr_write_mmio(host.host.mmio, dcr_n, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	else /* host.type == DCR_HOST_INVALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		WARN_ON(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EXPORT_SYMBOL_GPL(dcr_write_generic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif /* defined(CONFIG_PPC_DCR_NATIVE) && defined(CONFIG_PPC_DCR_MMIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int dcr_resource_start(const struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 				unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	unsigned int ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	const u32 *dr = of_get_property(np, "dcr-reg", &ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	if (dr == NULL || ds & 1 || index >= (ds / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return dr[index * 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) EXPORT_SYMBOL_GPL(dcr_resource_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int dcr_resource_len(const struct device_node *np, unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	unsigned int ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	const u32 *dr = of_get_property(np, "dcr-reg", &ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	if (dr == NULL || ds & 1 || index >= (ds / 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return dr[index * 2 + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) EXPORT_SYMBOL_GPL(dcr_resource_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #ifdef CONFIG_PPC_DCR_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static u64 of_translate_dcr_address(struct device_node *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 				    unsigned int dcr_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 				    unsigned int *out_stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	struct device_node *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	const u32 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	unsigned int stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	u64 ret = OF_BAD_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	dp = find_dcr_parent(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (dp == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		return OF_BAD_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	/* Stride is not properly defined yet, default to 0x10 for Axon */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	p = of_get_property(dp, "dcr-mmio-stride", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	stride = (p == NULL) ? 0x10 : *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	/* XXX FIXME: Which property name is to use of the 2 following ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	p = of_get_property(dp, "dcr-mmio-range", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	if (p == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		p = of_get_property(dp, "dcr-mmio-space", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (p == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	/* Maybe could do some better range checking here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ret = of_translate_address(dp, p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (ret != OF_BAD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		ret += (u64)(stride) * (u64)dcr_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (out_stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		*out_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	of_node_put(dp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dcr_host_mmio_t dcr_map_mmio(struct device_node *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			     unsigned int dcr_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			     unsigned int dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	dcr_host_mmio_t ret = { .token = NULL, .stride = 0, .base = dcr_n };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u64 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	pr_debug("dcr_map(%pOF, 0x%x, 0x%x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		 dev, dcr_n, dcr_c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	addr = of_translate_dcr_address(dev, dcr_n, &ret.stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	pr_debug("translates to addr: 0x%llx, stride: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		 (unsigned long long) addr, ret.stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	if (addr == OF_BAD_ADDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	pr_debug("mapping 0x%x bytes\n", dcr_c * ret.stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	ret.token = ioremap(addr, dcr_c * ret.stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	if (ret.token == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	pr_debug("mapped at 0x%p -> base is 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		 ret.token, ret.token - dcr_n * ret.stride);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	ret.token -= dcr_n * ret.stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) EXPORT_SYMBOL_GPL(dcr_map_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void dcr_unmap_mmio(dcr_host_mmio_t host, unsigned int dcr_c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	dcr_host_mmio_t h = host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (h.token == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	h.token += host.base * h.stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	iounmap(h.token);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	h.token = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) EXPORT_SYMBOL_GPL(dcr_unmap_mmio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #endif /* defined(CONFIG_PPC_DCR_MMIO) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef CONFIG_PPC_DCR_NATIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) DEFINE_SPINLOCK(dcr_ind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) EXPORT_SYMBOL_GPL(dcr_ind_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #endif	/* defined(CONFIG_PPC_DCR_NATIVE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)