Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _POWERPC_SYSDEV_DART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _POWERPC_SYSDEV_DART_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Offset from base to control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DART_CNTL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* Offset from base to exception register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DART_EXCP_U3	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Offset from base to TLB tag registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DART_TAGS_U3	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* U4 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DART_BASE_U4	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DART_SIZE_U4	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DART_EXCP_U4	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DART_TAGS_U4	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Control Register fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* U3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DART_CNTL_U3_BASE_MASK	0xfffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DART_CNTL_U3_BASE_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DART_CNTL_U3_FLUSHTLB	0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DART_CNTL_U3_ENABLE	0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DART_CNTL_U3_SIZE_MASK	0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DART_CNTL_U3_SIZE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* U4 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DART_BASE_U4_BASE_MASK	0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DART_BASE_U4_BASE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DART_CNTL_U4_ENABLE	0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DART_CNTL_U4_IONE	0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DART_CNTL_U4_FLUSHTLB	0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DART_CNTL_U4_IDLE	0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DART_CNTL_U4_PAR_EN	0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DART_CNTL_U4_IONE_MASK	0x07ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DART_SIZE_U4_SIZE_MASK	0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DART_SIZE_U4_SIZE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DART_REG(r)	(dart + ((r) >> 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DART_IN(r)	(in_be32(DART_REG(r)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DART_OUT(r,v)	(out_be32(DART_REG(r), (v)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* size of table in pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* DART table fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DARTMAP_VALID   0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DARTMAP_RPNMASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DART_PAGE_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DART_PAGE_SIZE		(1 << DART_PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #endif /* _POWERPC_SYSDEV_DART_H */