^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Common CPM code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2007-2008,2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Some parts derived from commproc.c/cpm2_common.c, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (c) 1999-2001 Dan Malek <dan@embeddedalley.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2000 MontaVista Software, Inc (source@mvista.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * 2006 (c) MontaVista Software, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Vitaly Bordug <vbordug@ru.mvista.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/udbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/cpm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <soc/fsl/qe/qe.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <mm/mmu_decl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static int __init cpm_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) np = of_find_compatible_node(NULL, NULL, "fsl,cpm2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) cpm_muram_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) subsys_initcall(cpm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #ifdef CONFIG_PPC_EARLY_DEBUG_CPM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static u32 __iomem *cpm_udbg_txdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static u8 __iomem *cpm_udbg_txbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static void udbg_putc_cpm(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (c == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) udbg_putc_cpm('\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) while (in_be32(&cpm_udbg_txdesc[0]) & 0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) out_8(cpm_udbg_txbuf, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) out_be32(&cpm_udbg_txdesc[0], 0xa0000001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) void __init udbg_init_cpm(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mmu_mapin_immr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) cpm_udbg_txdesc = (u32 __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (CONFIG_PPC_EARLY_DEBUG_CPM_ADDR - PHYS_IMMR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) VIRT_IMMR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) cpm_udbg_txbuf = (u8 __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (in_be32(&cpm_udbg_txdesc[1]) - PHYS_IMMR_BASE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) VIRT_IMMR_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) cpm_udbg_txdesc = (u32 __iomem __force *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) CONFIG_PPC_EARLY_DEBUG_CPM_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) cpm_udbg_txbuf = (u8 __iomem __force *)in_be32(&cpm_udbg_txdesc[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (cpm_udbg_txdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #ifdef CONFIG_CPM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) setbat(1, 0xf0000000, 0xf0000000, 1024*1024, PAGE_KERNEL_NCG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) udbg_putc = udbg_putc_cpm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #if defined(CONFIG_CPM2) || defined(CONFIG_8xx_GPIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct cpm2_ioports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 dir, par, sor, odr, dat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 res[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct cpm2_gpio32_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct of_mm_gpio_chip mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* shadowed data register to clear/set bits safely */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 cpdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static void cpm2_gpio32_save_regs(struct of_mm_gpio_chip *mm_gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct cpm2_gpio32_chip *cpm2_gc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) container_of(mm_gc, struct cpm2_gpio32_chip, mm_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct cpm2_ioports __iomem *iop = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) cpm2_gc->cpdata = in_be32(&iop->dat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int cpm2_gpio32_get(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct cpm2_ioports __iomem *iop = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pin_mask = 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return !!(in_be32(&iop->dat) & pin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void __cpm2_gpio32_set(struct of_mm_gpio_chip *mm_gc, u32 pin_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(&mm_gc->gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct cpm2_ioports __iomem *iop = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) cpm2_gc->cpdata |= pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) cpm2_gc->cpdata &= ~pin_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) out_be32(&iop->dat, cpm2_gc->cpdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static void cpm2_gpio32_set(struct gpio_chip *gc, unsigned int gpio, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 pin_mask = 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spin_lock_irqsave(&cpm2_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) __cpm2_gpio32_set(mm_gc, pin_mask, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) spin_unlock_irqrestore(&cpm2_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int cpm2_gpio32_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct cpm2_ioports __iomem *iop = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 pin_mask = 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spin_lock_irqsave(&cpm2_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) setbits32(&iop->dir, pin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) __cpm2_gpio32_set(mm_gc, pin_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) spin_unlock_irqrestore(&cpm2_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int cpm2_gpio32_dir_in(struct gpio_chip *gc, unsigned int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct cpm2_gpio32_chip *cpm2_gc = gpiochip_get_data(gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct cpm2_ioports __iomem *iop = mm_gc->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 pin_mask = 1 << (31 - gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) spin_lock_irqsave(&cpm2_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) clrbits32(&iop->dir, pin_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) spin_unlock_irqrestore(&cpm2_gc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int cpm2_gpiochip_add32(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct cpm2_gpio32_chip *cpm2_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct of_mm_gpio_chip *mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct gpio_chip *gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) cpm2_gc = kzalloc(sizeof(*cpm2_gc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (!cpm2_gc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) spin_lock_init(&cpm2_gc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) mm_gc = &cpm2_gc->mm_gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) gc = &mm_gc->gc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mm_gc->save_regs = cpm2_gpio32_save_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) gc->ngpio = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) gc->direction_input = cpm2_gpio32_dir_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) gc->direction_output = cpm2_gpio32_dir_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) gc->get = cpm2_gpio32_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) gc->set = cpm2_gpio32_set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) gc->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) gc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return of_mm_gpiochip_add_data(np, mm_gc, cpm2_gc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #endif /* CONFIG_CPM2 || CONFIG_8xx_GPIO */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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