^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Enter and leave sleep state on chips with 6xx-style HID0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * power management bits, which don't leave sleep state via reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Scott Wood <scottwood@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2006-2007 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) _GLOBAL(mpc6xx_enter_standby)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mflr r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) mfspr r5, SPRN_HID0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) rlwinm r5, r5, 0, ~(HID0_DOZE | HID0_NAP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) oris r5, r5, HID0_SLEEP@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) mtspr SPRN_HID0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) lis r5, ret_from_standby@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) ori r5, r5, ret_from_standby@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mtlr r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) lwz r6, TI_LOCAL_FLAGS(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) ori r6, r6, _TLF_SLEEPING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) stw r6, TI_LOCAL_FLAGS(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) mfmsr r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ori r5, r5, MSR_EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) oris r5, r5, MSR_POW@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) mtmsr r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 1: b 1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ret_from_standby:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mfspr r5, SPRN_HID0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) rlwinm r5, r5, 0, ~HID0_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) mtspr SPRN_HID0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) mtlr r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) blr