^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for PPC970-family processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Bits in event code for PPC970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PM_PMC_SH 12 /* PMC number (1-based) for direct events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PM_PMC_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM_UNIT_SH 8 /* TTMMUX number and setting - unit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PM_UNIT_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM_SPCSEL_SH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM_SPCSEL_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PM_BYTE_SH 4 /* Byte number of event bus to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PM_BYTE_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PM_PMCSEL_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Values in PM_UNIT field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PM_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PM_FPU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PM_VPU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PM_ISU 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PM_IFU 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PM_IDU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PM_STS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PM_LSU0 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PM_LSU1U 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM_LSU1L 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PM_LASTUNIT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * Bits in MMCR0 for PPC970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MMCR0_PMC1SEL_SH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMCR0_PMC2SEL_SH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMCR_PMCSEL_MSK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * Bits in MMCR1 for PPC970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMCR1_TTM0SEL_SH 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMCR1_TTM1SEL_SH 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMCR1_TTM3SEL_SH 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MMCR1_TTMSEL_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MMCR1_TD_CP_DBG0SEL_SH 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MMCR1_TD_CP_DBG1SEL_SH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMCR1_TD_CP_DBG2SEL_SH 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMCR1_TD_CP_DBG3SEL_SH 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMCR1_PMC1_ADDER_SEL_SH 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MMCR1_PMC2_ADDER_SEL_SH 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMCR1_PMC6_ADDER_SEL_SH 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MMCR1_PMC5_ADDER_SEL_SH 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MMCR1_PMC8_ADDER_SEL_SH 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MMCR1_PMC7_ADDER_SEL_SH 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMCR1_PMC3_ADDER_SEL_SH 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMCR1_PMC4_ADDER_SEL_SH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMCR1_PMC3SEL_SH 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMCR1_PMC4SEL_SH 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMCR1_PMC5SEL_SH 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MMCR1_PMC6SEL_SH 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMCR1_PMC7SEL_SH 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMCR1_PMC8SEL_SH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static short mmcr1_adder_bits[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MMCR1_PMC1_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MMCR1_PMC2_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MMCR1_PMC3_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MMCR1_PMC4_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MMCR1_PMC5_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MMCR1_PMC6_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MMCR1_PMC7_ADDER_SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MMCR1_PMC8_ADDER_SEL_SH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * Layout of constraint bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * 6666555555555544444444443333333333222222222211111111110000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 3210987654321098765432109876543210987654321098765432109876543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * <><><>[ >[ >[ >< >< >< >< ><><><><><><><><>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * SPT0T1 UC PS1 PS2 B0 B1 B2 B3 P1P2P3P4P5P6P7P8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * SP - SPCSEL constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 48-49: SPCSEL value 0x3_0000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * T0 - TTM0 constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * 46-47: TTM0SEL value (0=FPU, 2=IFU, 3=VPU) 0xC000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * T1 - TTM1 constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 44-45: TTM1SEL value (0=IDU, 3=STS) 0x3000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * UC - unit constraint: can't have all three of FPU|IFU|VPU, ISU, IDU|STS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 43: UC3 error 0x0800_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * 42: FPU|IFU|VPU events needed 0x0400_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * 41: ISU events needed 0x0200_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 40: IDU|STS events needed 0x0100_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * PS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * 39: PS1 error 0x0080_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * 36-38: count of events needing PMC1/2/5/6 0x0070_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * PS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * 35: PS2 error 0x0008_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 32-34: count of events needing PMC3/4/7/8 0x0007_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * 28-31: Byte 0 event source 0xf000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Encoding as for the event code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * B1, B2, B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * 24-27, 20-23, 16-19: Byte 1, 2, 3 event sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * 15: P1 error 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * 14-15: Count of events needing PMC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * P2..P8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * 0-13: Count of events needing PMC2..PMC8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned char direct_marked_event[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) (1<<2) | (1<<3), /* PMC1: PM_MRK_GRP_DISP, PM_MRK_ST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) (1<<3) | (1<<5), /* PMC2: PM_THRESH_TIMEO, PM_MRK_BRU_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) (1<<3) | (1<<5), /* PMC3: PM_MRK_ST_CMPL_INT, PM_MRK_VMX_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) (1<<4) | (1<<5), /* PMC4: PM_MRK_GRP_CMPL, PM_MRK_CRU_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) (1<<4) | (1<<5), /* PMC5: PM_GRP_MRK, PM_MRK_GRP_TIMEO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) (1<<3) | (1<<4) | (1<<5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* PMC6: PM_MRK_ST_STS, PM_MRK_FXU_FIN, PM_MRK_GRP_ISSUED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) (1<<4) | (1<<5), /* PMC7: PM_MRK_FPU_FIN, PM_MRK_INST_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) (1<<4) /* PMC8: PM_MRK_LSU_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Returns 1 if event counts things relating to marked instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int p970_marked_instr_event(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int pmc, psel, unit, byte, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) psel = event & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (direct_marked_event[pmc - 1] & (1 << psel))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (psel == 0) /* add events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bit = (pmc <= 4)? pmc - 1: 8 - pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else if (psel == 7 || psel == 13) /* decode events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bit = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bit = psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) switch (unit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case PM_VPU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mask = 0x4c; /* byte 0 bits 2,3,6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) case PM_LSU0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* byte 2 bits 0,2,3,4,6; all of byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mask = 0x085dff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case PM_LSU1L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) mask = 0x50 << 24; /* byte 3 bits 4,6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return (mask >> (byte * 8 + bit)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Masks and values for using events from the various units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [PM_ISU] = { 0x080000000000ull, 0x020000000000ull },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) [PM_IFU] = { 0xc80000000000ull, 0x840000000000ull },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) [PM_IDU] = { 0x380000000000ull, 0x010000000000ull },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [PM_STS] = { 0x380000000000ull, 0x310000000000ull },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int p970_get_constraint(u64 event, unsigned long *maskp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned long *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) int pmc, byte, unit, sh, spcsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) unsigned long mask = 0, value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int grp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (pmc > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sh = (pmc - 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) mask |= 2 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) value |= 1 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) grp = ((pmc - 1) >> 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (unit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) if (unit > PM_LASTUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) mask |= unit_cons[unit][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) value |= unit_cons[unit][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Bus events on bytes 0 and 2 can be counted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * on PMC1/2/5/6; bytes 1 and 3 on PMC3/4/7/8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (!pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) grp = byte & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Set byte lane select field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mask |= 0xfULL << (28 - 4 * byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) value |= (unsigned long)unit << (28 - 4 * byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (grp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* increment PMC1/2/5/6 field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mask |= 0x8000000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) value |= 0x1000000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) } else if (grp == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* increment PMC3/4/7/8 field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) mask |= 0x800000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) value |= 0x100000000ull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (spcsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) mask |= 3ull << 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) value |= (unsigned long)spcsel << 48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) *maskp = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) *valp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) alt[0] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* 2 alternatives for LSU empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (event == 0x2002 || event == 0x3002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) alt[1] = event ^ 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int p970_compute_mmcr(u64 event[], int n_ev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned int hwc[], struct mmcr_regs *mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct perf_event *pevents[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int pmc, unit, byte, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int ttm, grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) unsigned int pmc_inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned int pmc_grp_use[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned char busbyte[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned char unituse[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) unsigned char unitmap[] = { 0, 0<<3, 3<<3, 1<<3, 2<<3, 0|4, 3|4 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned char ttmuse[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned char pmcsel[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int spcsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) if (n_ev > 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* First pass to count resource use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pmc_grp_use[0] = pmc_grp_use[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) memset(busbyte, 0, sizeof(busbyte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) memset(unituse, 0, sizeof(unituse));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (pmc_inuse & (1 << (pmc - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) pmc_inuse |= 1 << (pmc - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* count 1/2/5/6 vs 3/4/7/8 use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) ++pmc_grp_use[((pmc - 1) >> 1) & 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (unit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (unit > PM_LASTUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) ++pmc_grp_use[byte & 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (busbyte[byte] && busbyte[byte] != unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) busbyte[byte] = unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unituse[unit] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (pmc_grp_use[0] > 4 || pmc_grp_use[1] > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Assign resources and set multiplexer selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * PM_ISU can go either on TTM0 or TTM1, but that's the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * choice we have to deal with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (unituse[PM_ISU] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_VPU]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) unitmap[PM_ISU] = 2 | 4; /* move ISU to TTM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Set TTM[01]SEL fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) ttmuse[0] = ttmuse[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) for (i = PM_FPU; i <= PM_STS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!unituse[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ttm = unitmap[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ++ttmuse[(ttm >> 2) & 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* Check only one unit per TTMx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (ttmuse[0] > 1 || ttmuse[1] > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Set byte lane select fields and TTM3SEL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) for (byte = 0; byte < 4; ++byte) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unit = busbyte[byte];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (unit <= PM_STS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ttm = (unitmap[unit] >> 2) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) else if (unit == PM_LSU0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ttm = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) ttm = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (unit == PM_LSU1L && byte >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) mmcr1 |= (unsigned long)ttm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) memset(pmcsel, 0x8, sizeof(pmcsel)); /* 8 means don't count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) psel = event[i] & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (!pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Bus event or any-PMC direct event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) psel |= 0x10 | ((byte & 2) << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) psel |= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (pmc = 0; pmc < 8; ++pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (pmc_inuse & (1 << pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) grp = (pmc >> 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (unit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (grp == (byte & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else if (pmc_grp_use[grp] < 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ++pmc_grp_use[grp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pmc_inuse |= 1 << pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Direct event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) --pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (psel == 0 && (byte & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* add events on higher-numbered bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) mmcr1 |= 1ull << mmcr1_adder_bits[pmc];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pmcsel[pmc] = psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) hwc[i] = pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) spcsel = (event[i] >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mmcr1 |= spcsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (p970_marked_instr_event(event[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mmcra |= MMCRA_SAMPLE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) for (pmc = 0; pmc < 2; ++pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) for (; pmc < 8; ++pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mmcr1 |= (unsigned long)pmcsel[pmc]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (pmc_inuse & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mmcr0 |= MMCR0_PMC1CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (pmc_inuse & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mmcr0 |= MMCR0_PMCjCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) mmcra |= 0x2000; /* mark only one IOP per PPC instruction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* Return MMCRx values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mmcr->mmcr0 = mmcr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) mmcr->mmcr1 = mmcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) mmcr->mmcra = mmcra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void p970_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * Setting the PMCxSEL field to 0x08 disables PMC x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (pmc <= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) shift = MMCR0_PMC1SEL_SH - 7 * pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) mmcr->mmcr0 = (mmcr->mmcr0 & ~(0x1fUL << shift)) | (0x08UL << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) shift = MMCR1_PMC3SEL_SH - 5 * (pmc - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) mmcr->mmcr1 = (mmcr->mmcr1 & ~(0x1fUL << shift)) | (0x08UL << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int ppc970_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) [PERF_COUNT_HW_CPU_CYCLES] = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) [PERF_COUNT_HW_INSTRUCTIONS] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) [PERF_COUNT_HW_CACHE_REFERENCES] = 0x8810, /* PM_LD_REF_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) [PERF_COUNT_HW_CACHE_MISSES] = 0x3810, /* PM_LD_MISS_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x431, /* PM_BR_ISSUED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) [PERF_COUNT_HW_BRANCH_MISSES] = 0x327, /* PM_GRP_BR_MPRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static u64 ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) [C(OP_READ)] = { 0x8810, 0x3810 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) [C(OP_WRITE)] = { 0x7810, 0x813 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) [C(OP_PREFETCH)] = { 0x731, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) [C(OP_READ)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) [C(OP_PREFETCH)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) [C(OP_READ)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) [C(OP_WRITE)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) [C(OP_PREFETCH)] = { 0x733, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) [C(OP_READ)] = { 0, 0x704 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) [C(OP_READ)] = { 0, 0x700 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) [C(OP_READ)] = { 0x431, 0x327 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [C(OP_READ)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static struct power_pmu ppc970_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .name = "PPC970/FX/MP",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .n_counter = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .max_alternatives = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .add_fields = 0x001100005555ull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .test_adder = 0x013300000000ull,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .compute_mmcr = p970_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .get_constraint = p970_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .get_alternatives = p970_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .disable_pmc = p970_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .n_generic = ARRAY_SIZE(ppc970_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .generic_events = ppc970_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .cache_events = &ppc970_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .flags = PPMU_NO_SIPR | PPMU_NO_CONT_SAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int init_ppc970_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) && strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/970MP")))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return register_power_pmu(&ppc970_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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