^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for POWER9 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2013 Michael Ellerman, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) "power9-pmu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include "isa207-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Raw event encoding for Power9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * 60 56 52 48 44 40 36 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | | [ ] [ ] [ thresh_cmp ] [ thresh_ctl ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | | *- IFM (Linux) | thresh start/stop -*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * | *- BHRB (Linux) *sm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * *- EBB (Linux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * 28 24 20 16 12 8 4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * [ ] [ sample ] [cache] [ pmc ] [unit ] [] m [ pmcxsel ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | | | | *- mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * | | *- L1/L2/L3 cache_sel |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * | *- sampling mode for marked events *- combine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * *- thresh_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Below uses IBM bit numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * MMCR1[x:y] = unit (PMCxUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * MMCR1[24] = pmc1combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * MMCR1[25] = pmc1combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * MMCR1[26] = pmc2combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * MMCR1[27] = pmc2combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * MMCR1[28] = pmc3combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * MMCR1[29] = pmc3combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * MMCR1[30] = pmc4combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * MMCR1[31] = pmc4combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * MMCR1[20:27] = thresh_ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * MMCR1[20:27] = thresh_ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * MMCRA[48:55] = thresh_ctl (THRESH START/END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * if thresh_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * MMCRA[45:47] = thresh_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * if thresh_cmp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * MMCRA[9:11] = thresh_cmp[0:2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * MMCRA[12:18] = thresh_cmp[3:9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * MMCR1[16] = cache_sel[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * MMCR1[17] = cache_sel[3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * if mark:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * MMCRA[63] = 1 (SAMPLE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * if EBB and BHRB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * MMCRA[32:33] = IFM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * MMCRA[SDAR_MODE] = sm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Some power9 event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EVENT(_name, _code) _name = _code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include "power9-events-list.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* MMCRA IFM bits - POWER9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define POWER9_MMCRA_IFM1 0x0000000040000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define POWER9_MMCRA_IFM2 0x0000000080000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define POWER9_MMCRA_IFM3 0x00000000C0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define POWER9_MMCRA_BHRB_MASK 0x00000000C0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) extern u64 PERF_REG_EXTENDED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Nasty Power9 specific hack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PVR_POWER9_CUMULUS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* PowerISA v2.07 format attribute structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) extern struct attribute_group isa207_pmu_format_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int p9_dd21_bl_ev[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PM_MRK_ST_DONE_L2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PM_RADIX_PWC_L1_HIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PM_FLOP_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) PM_MRK_NTF_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PM_RADIX_PWC_L2_HIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PM_IFETCH_THROTTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PM_MRK_L2_TM_ST_ABORT_SISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PM_RADIX_PWC_L3_HIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PM_RUN_CYC_SMT2_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PM_TM_TX_PASS_RUN_INST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PM_DISP_HELD_SYNC_HOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int p9_dd22_bl_ev[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PM_DTLB_MISS_16G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) PM_DERAT_MISS_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) PM_DTLB_MISS_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PM_MRK_DTLB_MISS_1G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PM_DTLB_MISS_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PM_DERAT_MISS_1G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PM_MRK_DERAT_MISS_2M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PM_MRK_DTLB_MISS_4K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PM_MRK_DTLB_MISS_16G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PM_DTLB_MISS_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PM_MRK_DERAT_MISS_1G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PM_MRK_DTLB_MISS_64K,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PM_DISP_HELD_SYNC_HOLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PM_DTLB_MISS_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PM_DTLB_MISS_1G,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PM_MRK_DTLB_MISS_16M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Table of alternatives, sorted by column 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const unsigned int power9_event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { PM_INST_DISP, PM_INST_DISP_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { PM_RUN_CYC_ALT, PM_RUN_CYC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { PM_LD_MISS_L1, PM_LD_MISS_L1_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { PM_BR_2PATH, PM_BR_2PATH_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static int power9_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int num_alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) num_alt = isa207_get_alternatives(event, alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ARRAY_SIZE(power9_event_alternatives), flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) power9_event_alternatives);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return num_alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_ICT_NOSLOT_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1_FIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) CACHE_EVENT_ATTR(LLC-prefetches, PM_L3_PREF_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static struct attribute *power9_events_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) GENERIC_EVENT_PTR(PM_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) GENERIC_EVENT_PTR(PM_ICT_NOSLOT_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) GENERIC_EVENT_PTR(PM_CMPLU_STALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) GENERIC_EVENT_PTR(PM_INST_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) GENERIC_EVENT_PTR(PM_BR_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) GENERIC_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) GENERIC_EVENT_PTR(PM_LD_MISS_L1_FIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) GENERIC_EVENT_PTR(MEM_LOADS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) GENERIC_EVENT_PTR(MEM_STORES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) CACHE_EVENT_PTR(PM_LD_MISS_L1_FIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) CACHE_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) CACHE_EVENT_PTR(PM_L1_PREF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) CACHE_EVENT_PTR(PM_ST_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) CACHE_EVENT_PTR(PM_INST_FROM_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CACHE_EVENT_PTR(PM_DATA_FROM_L3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CACHE_EVENT_PTR(PM_L3_PREF_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) CACHE_EVENT_PTR(PM_BR_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) CACHE_EVENT_PTR(PM_DTLB_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CACHE_EVENT_PTR(PM_ITLB_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static struct attribute_group power9_pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .attrs = power9_events_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) PMU_FORMAT_ATTR(event, "config:0-51");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) PMU_FORMAT_ATTR(mark, "config:8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PMU_FORMAT_ATTR(combine, "config:10-11");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) PMU_FORMAT_ATTR(unit, "config:12-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PMU_FORMAT_ATTR(pmc, "config:16-19");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) PMU_FORMAT_ATTR(cache_sel, "config:20-23");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PMU_FORMAT_ATTR(sample_mode, "config:24-28");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) PMU_FORMAT_ATTR(thresh_start, "config:36-39");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) PMU_FORMAT_ATTR(thresh_cmp, "config:40-49");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PMU_FORMAT_ATTR(sdar_mode, "config:50-51");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static struct attribute *power9_pmu_format_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) &format_attr_pmcxsel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) &format_attr_mark.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) &format_attr_combine.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) &format_attr_unit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) &format_attr_pmc.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) &format_attr_cache_sel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) &format_attr_sample_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) &format_attr_thresh_sel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) &format_attr_thresh_stop.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) &format_attr_thresh_start.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) &format_attr_thresh_cmp.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) &format_attr_sdar_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct attribute_group power9_pmu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .attrs = power9_pmu_format_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct attribute_group *power9_pmu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) &power9_pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) &power9_pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static int power9_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static u64 power9_bhrb_filter_map(u64 branch_sample_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u64 pmu_bhrb_filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* BHRB and regular PMU events share the same privilege state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * filter configuration. BHRB is always recorded along with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * regular PMU event. As the privilege state filter is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * in the basic PMC configuration of the accompanying regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * PMU event, we ignore any separate BHRB specific request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* No branch filter requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Invalid branch filter options - HW does not support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pmu_bhrb_filter |= POWER9_MMCRA_IFM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Every thing else is unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void power9_config_bhrb(u64 pmu_bhrb_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) pmu_bhrb_filter &= POWER9_MMCRA_BHRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Enable BHRB filter in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static u64 power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [ C(L1D) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [ C(RESULT_MISS) ] = PM_LD_MISS_L1_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [ C(RESULT_MISS) ] = PM_ST_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [ C(RESULT_ACCESS) ] = PM_L1_PREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [ C(L1I) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [ C(RESULT_MISS) ] = PM_L1_ICACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [ C(LL) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [ C(RESULT_MISS) ] = PM_DATA_FROM_L3MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) [ C(DTLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [ C(RESULT_MISS) ] = PM_DTLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [ C(ITLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [ C(RESULT_MISS) ] = PM_ITLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) [ C(BPU) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) [ C(RESULT_ACCESS) ] = PM_BR_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) [ C(RESULT_MISS) ] = PM_BR_MPRED_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) [ C(NODE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #undef C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static struct power_pmu power9_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "POWER9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .n_counter = MAX_PMU_COUNTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .add_fields = ISA207_ADD_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .test_adder = ISA207_TEST_ADDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .group_constraint_mask = CNST_CACHE_PMC4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .group_constraint_val = CNST_CACHE_PMC4_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .compute_mmcr = isa207_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .config_bhrb = power9_config_bhrb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .bhrb_filter_map = power9_bhrb_filter_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .get_constraint = isa207_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .get_alternatives = power9_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .get_mem_data_src = isa207_get_mem_data_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .get_mem_weight = isa207_get_mem_weight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .disable_pmc = isa207_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .n_generic = ARRAY_SIZE(power9_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .generic_events = power9_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .cache_events = &power9_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .attr_groups = power9_pmu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .bhrb_nr = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .capabilities = PERF_PMU_CAP_EXTENDED_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int init_power9_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int pvr = mfspr(SPRN_PVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Comes from cpu_specs[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Blacklist events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (!(pvr & PVR_POWER9_CUMULUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) power9_pmu.blacklist_ev = p9_dd21_bl_ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) power9_pmu.blacklist_ev = p9_dd22_bl_ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd22_bl_ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Set the PERF_REG_EXTENDED_MASK here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) rc = register_power_pmu(&power9_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Tell userspace that EBB is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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