Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Performance counter support for POWER8 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2013 Michael Ellerman, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define pr_fmt(fmt)	"power8-pmu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include "isa207-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * Some power8 event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define EVENT(_name, _code)	_name = _code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "power8-events-list.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) /* MMCRA IFM bits - POWER8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	POWER8_MMCRA_IFM1		0x0000000040000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	POWER8_MMCRA_IFM2		0x0000000080000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	POWER8_MMCRA_IFM3		0x00000000C0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	POWER8_MMCRA_BHRB_MASK		0x00000000C0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * Raw event encoding for PowerISA v2.07 (Power8):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *        60        56        52        48        44        40        36        32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *   | | [ ]                           [      thresh_cmp     ]   [  thresh_ctl   ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *   | |  |                                                              |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *   | |  *- IFM (Linux)                 thresh start/stop OR FAB match -*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *   | *- BHRB (Linux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *   *- EBB (Linux)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *        28        24        20        16        12         8         4         0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  *   [   ] [  sample ]   [cache]   [ pmc ]   [unit ]   c     m   [    pmcxsel    ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  *     |        |           |                          |     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  *     |        |           |                          |     *- mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46)  *     |        |           *- L1/L2/L3 cache_sel      |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47)  *     |        |                                      |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48)  *     |        *- sampling mode for marked events     *- combine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  *     |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  *     *- thresh_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * Below uses IBM bit numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * MMCR1[x:y] = unit    (PMCxUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * MMCR1[x]   = combine (PMCxCOMB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  *	# PM_MRK_FAB_RSP_MATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  *	MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	# PM_MRK_FAB_RSP_MATCH_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *	MMCR1[20:27] = thresh_ctl   (FAB_CRESP_MATCH / FAB_TYPE_MATCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *	MMCRA[48:55] = thresh_ctl   (THRESH START/END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * if thresh_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	MMCRA[45:47] = thresh_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * if thresh_cmp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *	MMCRA[22:24] = thresh_cmp[0:2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  *	MMCRA[25:31] = thresh_cmp[3:9]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  * if unit == 6 or unit == 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  *	MMCRC[53:55] = cache_sel[1:3]      (L2EVENT_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * else if unit == 8 or unit == 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  *	if cache_sel[0] == 0: # L3 bank
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77)  *		MMCRC[47:49] = cache_sel[1:3]  (L3EVENT_SEL0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78)  *	else if cache_sel[0] == 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79)  *		MMCRC[50:51] = cache_sel[2:3]  (L3EVENT_SEL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80)  * else if cache_sel[1]: # L1 event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  *	MMCR1[16] = cache_sel[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  *	MMCR1[17] = cache_sel[3]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84)  * if mark:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85)  *	MMCRA[63]    = 1		(SAMPLE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86)  *	MMCRA[57:59] = sample[0:2]	(RAND_SAMP_ELIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  *	MMCRA[61:62] = sample[3:4]	(RAND_SAMP_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89)  * if EBB and BHRB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90)  *	MMCRA[32:33] = IFM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /* PowerISA v2.07 format attribute structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) extern struct attribute_group isa207_pmu_format_group;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* Table of alternatives, sorted by column 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static const unsigned int event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{ PM_MRK_ST_CMPL,		PM_MRK_ST_CMPL_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{ PM_BR_MRK_2PATH,		PM_BR_MRK_2PATH_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{ PM_L3_CO_MEPF,		PM_L3_CO_MEPF_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{ PM_MRK_DATA_FROM_L2MISS,	PM_MRK_DATA_FROM_L2MISS_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{ PM_CMPLU_STALL_ALT,		PM_CMPLU_STALL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{ PM_BR_2PATH,			PM_BR_2PATH_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{ PM_INST_DISP,			PM_INST_DISP_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{ PM_RUN_CYC_ALT,		PM_RUN_CYC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{ PM_MRK_FILT_MATCH,		PM_MRK_FILT_MATCH_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{ PM_LD_MISS_L1,		PM_LD_MISS_L1_ALT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{ PM_RUN_INST_CMPL_ALT,		PM_RUN_INST_CMPL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static int power8_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int num_alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	num_alt = isa207_get_alternatives(event, alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 					  ARRAY_SIZE(event_alternatives), flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 					  event_alternatives);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return num_alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) GENERIC_EVENT_ATTR(cpu-cycles,			PM_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) GENERIC_EVENT_ATTR(stalled-cycles-frontend,	PM_GCT_NOSLOT_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) GENERIC_EVENT_ATTR(stalled-cycles-backend,	PM_CMPLU_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) GENERIC_EVENT_ATTR(instructions,		PM_INST_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) GENERIC_EVENT_ATTR(branch-instructions,		PM_BRU_FIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) GENERIC_EVENT_ATTR(branch-misses,		PM_BR_MPRED_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GENERIC_EVENT_ATTR(cache-references,		PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) GENERIC_EVENT_ATTR(cache-misses,		PM_LD_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) GENERIC_EVENT_ATTR(mem_access,			MEM_ACCESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) CACHE_EVENT_ATTR(L1-dcache-load-misses,		PM_LD_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CACHE_EVENT_ATTR(L1-dcache-loads,		PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CACHE_EVENT_ATTR(L1-dcache-prefetches,		PM_L1_PREF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CACHE_EVENT_ATTR(L1-dcache-store-misses,	PM_ST_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CACHE_EVENT_ATTR(L1-icache-load-misses,		PM_L1_ICACHE_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CACHE_EVENT_ATTR(L1-icache-loads,		PM_INST_FROM_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CACHE_EVENT_ATTR(L1-icache-prefetches,		PM_IC_PREF_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CACHE_EVENT_ATTR(LLC-load-misses,		PM_DATA_FROM_L3MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CACHE_EVENT_ATTR(LLC-loads,			PM_DATA_FROM_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CACHE_EVENT_ATTR(LLC-prefetches,		PM_L3_PREF_ALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CACHE_EVENT_ATTR(LLC-store-misses,		PM_L2_ST_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CACHE_EVENT_ATTR(LLC-stores,			PM_L2_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CACHE_EVENT_ATTR(branch-load-misses,		PM_BR_MPRED_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CACHE_EVENT_ATTR(branch-loads,			PM_BRU_FIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CACHE_EVENT_ATTR(dTLB-load-misses,		PM_DTLB_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CACHE_EVENT_ATTR(iTLB-load-misses,		PM_ITLB_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static struct attribute *power8_events_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	GENERIC_EVENT_PTR(PM_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	GENERIC_EVENT_PTR(PM_CMPLU_STALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	GENERIC_EVENT_PTR(PM_INST_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	GENERIC_EVENT_PTR(PM_BRU_FIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	GENERIC_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	GENERIC_EVENT_PTR(PM_LD_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	GENERIC_EVENT_PTR(MEM_ACCESS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	CACHE_EVENT_PTR(PM_LD_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	CACHE_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	CACHE_EVENT_PTR(PM_L1_PREF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	CACHE_EVENT_PTR(PM_ST_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	CACHE_EVENT_PTR(PM_INST_FROM_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	CACHE_EVENT_PTR(PM_IC_PREF_WRITE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	CACHE_EVENT_PTR(PM_DATA_FROM_L3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	CACHE_EVENT_PTR(PM_L3_PREF_ALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	CACHE_EVENT_PTR(PM_L2_ST_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	CACHE_EVENT_PTR(PM_L2_ST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	CACHE_EVENT_PTR(PM_BRU_FIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	CACHE_EVENT_PTR(PM_DTLB_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	CACHE_EVENT_PTR(PM_ITLB_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static struct attribute_group power8_pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.attrs = power8_events_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) static const struct attribute_group *power8_pmu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	&isa207_pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	&power8_pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int power8_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	[PERF_COUNT_HW_CPU_CYCLES] =			PM_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] =	PM_GCT_NOSLOT_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	[PERF_COUNT_HW_STALLED_CYCLES_BACKEND] =	PM_CMPLU_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	[PERF_COUNT_HW_INSTRUCTIONS] =			PM_INST_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =		PM_BRU_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	[PERF_COUNT_HW_BRANCH_MISSES] =			PM_BR_MPRED_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	[PERF_COUNT_HW_CACHE_REFERENCES] =		PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	[PERF_COUNT_HW_CACHE_MISSES] =			PM_LD_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static u64 power8_bhrb_filter_map(u64 branch_sample_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	u64 pmu_bhrb_filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	/* BHRB and regular PMU events share the same privilege state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	 * filter configuration. BHRB is always recorded along with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	 * regular PMU event. As the privilege state filter is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * in the basic PMC configuration of the accompanying regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	 * PMU event, we ignore any separate BHRB specific request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* No branch filter requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	/* Invalid branch filter options - HW does not support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		pmu_bhrb_filter |= POWER8_MMCRA_IFM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	/* Every thing else is unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void power8_config_bhrb(u64 pmu_bhrb_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	pmu_bhrb_filter &= POWER8_MMCRA_BHRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	/* Enable BHRB filter in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define C(x)	PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static u64 power8_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	[ C(L1D) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 			[ C(RESULT_ACCESS) ] = PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			[ C(RESULT_MISS)   ] = PM_LD_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			[ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 			[ C(RESULT_MISS)   ] = PM_ST_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			[ C(RESULT_ACCESS) ] = PM_L1_PREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			[ C(RESULT_MISS)   ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	[ C(L1I) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			[ C(RESULT_ACCESS) ] = PM_INST_FROM_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			[ C(RESULT_MISS)   ] = PM_L1_ICACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			[ C(RESULT_ACCESS) ] = PM_L1_DEMAND_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			[ C(RESULT_ACCESS) ] = PM_IC_PREF_WRITE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			[ C(RESULT_MISS)   ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	[ C(LL) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			[ C(RESULT_ACCESS) ] = PM_DATA_FROM_L3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			[ C(RESULT_MISS)   ] = PM_DATA_FROM_L3MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			[ C(RESULT_ACCESS) ] = PM_L2_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			[ C(RESULT_MISS)   ] = PM_L2_ST_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			[ C(RESULT_ACCESS) ] = PM_L3_PREF_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 			[ C(RESULT_MISS)   ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	[ C(DTLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			[ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			[ C(RESULT_MISS)   ] = PM_DTLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	[ C(ITLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 			[ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			[ C(RESULT_MISS)   ] = PM_ITLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	[ C(BPU) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			[ C(RESULT_ACCESS) ] = PM_BRU_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			[ C(RESULT_MISS)   ] = PM_BR_MPRED_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	[ C(NODE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		[ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		[ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		[ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			[ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			[ C(RESULT_MISS)   ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #undef C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static struct power_pmu power8_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	.name			= "POWER8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	.n_counter		= MAX_PMU_COUNTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	.max_alternatives	= MAX_ALT + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	.add_fields		= ISA207_ADD_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	.test_adder		= ISA207_TEST_ADDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	.compute_mmcr		= isa207_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.config_bhrb		= power8_config_bhrb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	.bhrb_filter_map	= power8_bhrb_filter_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	.get_constraint		= isa207_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	.get_alternatives	= power8_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.get_mem_data_src	= isa207_get_mem_data_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.get_mem_weight		= isa207_get_mem_weight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.disable_pmc		= isa207_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	.flags			= PPMU_HAS_SIER | PPMU_ARCH_207S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	.n_generic		= ARRAY_SIZE(power8_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	.generic_events		= power8_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.cache_events		= &power8_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.attr_groups		= power8_pmu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.bhrb_nr		= 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int init_power8_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power8"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	rc = register_power_pmu(&power8_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	/* Tell userspace that EBB is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	if (cpu_has_feature(CPU_FTR_PMAO_BUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		pr_info("PMAO restore workaround active.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }