^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for POWER7 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Bits in event code for POWER7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PM_PMC_SH 16 /* PMC number (1-based) for direct events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM_PMC_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM_UNIT_SH 12 /* TTMMUX number and setting - unit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM_UNIT_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PM_COMBINE_SH 11 /* Combined event bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PM_COMBINE_MSK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PM_COMBINE_MSKS 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PM_L2SEL_SH 8 /* L2 event select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PM_L2SEL_MSK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PM_PMCSEL_MSK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Bits in MMCR1 for POWER7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MMCR1_TTM0SEL_SH 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MMCR1_TTM1SEL_SH 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MMCR1_TTM2SEL_SH 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MMCR1_TTM3SEL_SH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MMCR1_TTMSEL_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MMCR1_L2SEL_SH 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MMCR1_L2SEL_MSK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MMCR1_PMC1_COMBINE_SH 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MMCR1_PMC2_COMBINE_SH 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MMCR1_PMC3_COMBINE_SH 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MMCR1_PMC4_COMBINE_SH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMCR1_PMC1SEL_SH 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMCR1_PMC2SEL_SH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMCR1_PMC3SEL_SH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMCR1_PMC4SEL_SH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMCR1_PMCSEL_MSK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Power7 event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EVENT(_name, _code) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) _name = _code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include "power7-events-list.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * Layout of constraint bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * 6666555555555544444444443333333333222222222211111111110000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * 3210987654321098765432109876543210987654321098765432109876543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * < >< ><><><><><><>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * L2 NC P6P5P4P3P2P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * L2 - 16-18 - Required L2SEL value (select field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * NC - number of counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * 15: NC error 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * 12-14: number of events needing PMC1-4 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * P6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 11: P6 error 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * 10-11: Count of events needing PMC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * P1..P5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * 0-9: Count of events needing PMC1..PMC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int power7_get_constraint(u64 event, unsigned long *maskp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned long *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int pmc, sh, unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned long mask = 0, value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (pmc > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sh = (pmc - 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) mask |= 2 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) value |= 1 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (pmc >= 5 && !(event == 0x500fa || event == 0x600f4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (pmc < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* need a counter from PMC1-4 set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mask |= 0x8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) value |= 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (unit == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* L2SEL must be identical across events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int l2sel = (event >> PM_L2SEL_SH) & PM_L2SEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) mask |= 0x7 << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) value |= l2sel << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) *maskp = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *valp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MAX_ALT 2 /* at most 2 alternatives for any event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const unsigned int event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { 0x200f2, 0x300f2 }, /* PM_INST_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { 0x200f4, 0x600f4 }, /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x400fa, 0x500fa }, /* PM_RUN_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * Scan the alternatives table for a match and return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * index into the alternatives table if found, else -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int find_alternative(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (event < event_alternatives[i][0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (event == event_alternatives[i][j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static s64 find_alternative_decode(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int pmc, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* this only handles the 4x decode events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) psel = event & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if ((pmc == 2 || pmc == 4) && (psel & ~7) == 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return event - (1 << PM_PMC_SH) + 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if ((pmc == 1 || pmc == 3) && (psel & ~7) == 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return event + (1 << PM_PMC_SH) - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int power7_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int i, j, nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) s64 ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) alt[0] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) i = find_alternative(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) for (j = 0; j < MAX_ALT; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ae = event_alternatives[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ae && ae != event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) alt[nalt++] = ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ae = find_alternative_decode(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ae > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) alt[nalt++] = ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (flags & PPMU_ONLY_COUNT_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * We're only counting in RUN state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * so PM_CYC is equivalent to PM_RUN_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * and PM_INST_CMPL === PM_RUN_INST_CMPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * This doesn't include alternatives that don't provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * any extra flexibility in assigning PMCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) j = nalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < nalt; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) switch (alt[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case 0x1e: /* PM_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) alt[j++] = 0x600f4; /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case 0x600f4: /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) alt[j++] = 0x1e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) case 0x2: /* PM_PPC_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) alt[j++] = 0x500fa; /* PM_RUN_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case 0x500fa: /* PM_RUN_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) alt[j++] = 0x2; /* PM_PPC_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) nalt = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return nalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * Returns 1 if event counts things relating to marked instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int power7_marked_instr_event(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int pmc, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) psel = event & PM_PMCSEL_MSK & ~1; /* trim off edge/level bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (pmc >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) switch (psel >> 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return pmc == 2 || pmc == 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (psel == 0x3c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return pmc == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (psel == 0x3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return pmc != 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return unit == 0xd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) if (psel == 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return pmc >= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return unit == 0xd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int power7_compute_mmcr(u64 event[], int n_ev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int hwc[], struct mmcr_regs *mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct perf_event *pevents[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) unsigned long mmcr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned int pmc, unit, combine, l2sel, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) unsigned int pmc_inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* First pass to count resource use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (pmc > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (pmc_inuse & (1 << (pmc - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) pmc_inuse |= 1 << (pmc - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Second pass: assign PMCs, set all MMCR1 fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) combine = (event[i] >> PM_COMBINE_SH) & PM_COMBINE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) l2sel = (event[i] >> PM_L2SEL_SH) & PM_L2SEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) psel = event[i] & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Bus event or any-PMC direct event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) for (pmc = 0; pmc < 4; ++pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (!(pmc_inuse & (1 << pmc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (pmc >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) pmc_inuse |= 1 << pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Direct or decoded event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) --pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (pmc <= 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mmcr1 |= (unsigned long) unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) << (MMCR1_TTM0SEL_SH - 4 * pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mmcr1 |= (unsigned long) combine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) << (MMCR1_PMC1_COMBINE_SH - pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (unit == 6) /* L2 events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mmcr1 |= (unsigned long) l2sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) << MMCR1_L2SEL_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (power7_marked_instr_event(event[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) mmcra |= MMCRA_SAMPLE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) hwc[i] = pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Return MMCRx values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) mmcr->mmcr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (pmc_inuse & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) mmcr->mmcr0 = MMCR0_PMC1CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (pmc_inuse & 0x3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) mmcr->mmcr0 |= MMCR0_PMCjCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) mmcr->mmcr1 = mmcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) mmcr->mmcra = mmcra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static void power7_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (pmc <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int power7_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_GCT_NOSLOT_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BRU_FIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static u64 power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) [C(OP_READ)] = { 0xc880, 0x400f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [C(OP_WRITE)] = { 0, 0x300f0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [C(OP_PREFETCH)] = { 0xd8b8, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [C(OP_READ)] = { 0, 0x200fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [C(OP_PREFETCH)] = { 0x408a, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [C(OP_READ)] = { 0x16080, 0x26080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [C(OP_WRITE)] = { 0x16082, 0x26082 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [C(OP_PREFETCH)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [C(OP_READ)] = { 0, 0x300fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [C(OP_READ)] = { 0, 0x400fc },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [C(OP_READ)] = { 0x10068, 0x400f6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [C(OP_READ)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) GENERIC_EVENT_ATTR(stalled-cycles-frontend, PM_GCT_NOSLOT_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) GENERIC_EVENT_ATTR(stalled-cycles-backend, PM_CMPLU_STALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) GENERIC_EVENT_ATTR(branch-instructions, PM_BRU_FIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define EVENT(_name, _code) POWER_EVENT_ATTR(_name, _name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #include "power7-events-list.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define EVENT(_name, _code) POWER_EVENT_PTR(_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static struct attribute *power7_events_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) GENERIC_EVENT_PTR(PM_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) GENERIC_EVENT_PTR(PM_GCT_NOSLOT_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) GENERIC_EVENT_PTR(PM_CMPLU_STALL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) GENERIC_EVENT_PTR(PM_INST_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) GENERIC_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) GENERIC_EVENT_PTR(PM_LD_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) GENERIC_EVENT_PTR(PM_BRU_FIN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) GENERIC_EVENT_PTR(PM_BR_MPRED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #include "power7-events-list.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static struct attribute_group power7_pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .attrs = power7_events_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) PMU_FORMAT_ATTR(event, "config:0-19");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct attribute *power7_pmu_format_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static struct attribute_group power7_pmu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .attrs = power7_pmu_format_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static const struct attribute_group *power7_pmu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) &power7_pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) &power7_pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct power_pmu power7_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .name = "POWER7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .n_counter = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .max_alternatives = MAX_ALT + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .add_fields = 0x1555ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .test_adder = 0x3000ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .compute_mmcr = power7_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .get_constraint = power7_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .get_alternatives = power7_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .disable_pmc = power7_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .flags = PPMU_ALT_SIPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .attr_groups = power7_pmu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .n_generic = ARRAY_SIZE(power7_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .generic_events = power7_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .cache_events = &power7_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int init_power7_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power7"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (pvr_version_is(PVR_POWER7p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) power7_pmu.flags |= PPMU_SIAR_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return register_power_pmu(&power7_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags