^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for POWER6 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Bits in event code for POWER6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM_PMC_MSK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM_UNIT_SH 16 /* Unit event comes (TTMxSEL encoding) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM_UNIT_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PM_UNIT_MSKS (PM_UNIT_MSK << PM_UNIT_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PM_LLAV 0x8000 /* Load lookahead match value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PM_LLA 0x4000 /* Load lookahead match enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PM_BYTE_SH 12 /* Byte of event bus to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PM_BYTE_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PM_SUBUNIT_SH 8 /* Subunit event comes from (NEST_SEL enc.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PM_SUBUNIT_MSK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PM_PMCSEL_MSK 0xff /* PMCxSEL value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PM_BUSEVENT_MSK 0xf3700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Bits in MMCR1 for POWER6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MMCR1_TTM0SEL_SH 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MMCR1_TTMSEL_SH(n) (MMCR1_TTM0SEL_SH - (n) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MMCR1_TTMSEL_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MMCR1_TTMSEL(m, n) (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MMCR1_NESTSEL_SH 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MMCR1_NESTSEL_MSK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MMCR1_PMC1_LLA (1ul << 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMCR1_PMC1_LLA_VALUE (1ul << 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMCR1_PMC1_ADDR_SEL (1ul << 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMCR1_PMC1SEL_SH 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMCR1_PMCSEL_MSK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Map of which direct events on which PMCs are marked instruction events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * Indexed by PMCSEL value >> 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Bottom 4 bits are a map of which PMCs are interesting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * top 4 bits say what sort of event:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * 0 = direct marked event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 1 = byte decode event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * 4 = add/and event (PMC1 -> bits 0 & 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 5 = add/and event (PMC1 -> bits 1 & 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * 6 = add/and event (PMC1 -> bits 2 & 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 7 = add/and event (PMC1 -> bits 3 & 7).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static unsigned char direct_event_is_marked[0x60 >> 1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 0, /* 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 0, /* 02 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0, /* 04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 0x07, /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 0x04, /* 08 PM_MRK_DFU_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 0x06, /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 0, /* 0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 0, /* 0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 0x02, /* 10 PM_MRK_INST_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 0x08, /* 12 PM_MRK_LSU_DERAT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 0, /* 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 0, /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 0x0c, /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 0x0f, /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 0x01, /* 1c PM_MRK_INST_ISSUED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0, /* 1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 0, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 0, /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 0, /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 0, /* 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 0x15, /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 0, /* 2a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 0, /* 2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 0, /* 2e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 0x4f, /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 0x7f, /* 32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 0x4f, /* 34 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) 0x5f, /* 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 0x6f, /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) 0x4f, /* 3a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 0, /* 3c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 0x08, /* 3e PM_MRK_INST_TIMEO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 0x1f, /* 40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 0x1f, /* 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 0x1f, /* 44 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x1f, /* 46 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x1f, /* 48 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x1f, /* 4a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x1f, /* 4c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x1f, /* 4e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0, /* 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x05, /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x1c, /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x02, /* 56 PM_MRK_LD_MISS_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0, /* 58 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0, /* 5a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0, /* 5c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0, /* 5e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Masks showing for each unit which bits are marked events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static u32 marked_bus_events[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x01000000, /* direct events set 1: byte 3 bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x00010000, /* direct events set 2: byte 2 bit 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0, 0, 0, 0, /* IDU, IFU, nest: nothing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x00000088, /* VMX set 1: byte 0 bits 3, 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x000000c0, /* VMX set 2: byte 0 bits 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0xff010000u, /* LSU set 2: byte 2 bit 0, all of byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0, /* LSU set 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x00000010, /* VMX set 3: byte 0 bit 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0, /* BFP set 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x00000022, /* BFP set 2: byte 0 bits 1, 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Returns 1 if event counts things relating to marked instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int power6_marked_instr_event(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int pmc, psel, ptype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int bit, byte, unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) psel = (event & PM_PMCSEL_MSK) >> 1; /* drop edge/level bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (pmc >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (psel < sizeof(direct_event_is_marked)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ptype = direct_event_is_marked[psel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ptype >>= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (ptype == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ptype == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bit = ptype ^ (pmc - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) } else if ((psel & 0x48) == 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bit = psel & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (!(event & PM_BUSEVENT_MSK) || bit == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mask = marked_bus_events[unit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return (mask >> (byte * 8 + bit)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Assign PMC numbers and compute MMCR1 value for a set of events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int p6_compute_mmcr(u64 event[], int n_ev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long mmcr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int pmc, ev, b, u, s, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int ttmset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int pmc_inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (n_ev > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (pmc_inuse & (1 << (pmc - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return -1; /* collision! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) pmc_inuse |= 1 << (pmc - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ev = event[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) --pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* can go on any PMC; find a free one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) for (pmc = 0; pmc < 4; ++pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (!(pmc_inuse & (1 << pmc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (pmc >= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pmc_inuse |= 1 << pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) hwc[i] = pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) psel = ev & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ev & PM_BUSEVENT_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* this event uses the event bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* check for conflict on this byte of event bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ttmset |= 1 << b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (u == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Nest events have a further mux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if ((ttmset & 0x10) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MMCR1_NESTSEL(mmcr1) != s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) ttmset |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (0x30 <= psel && psel <= 0x3d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* these need the PMCx_ADDR_SEL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (b >= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* bus select values are different for PMC3/4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (pmc >= 2 && (psel & 0x90) == 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) psel ^= 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (ev & PM_LLA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mmcr1 |= MMCR1_PMC1_LLA >> pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) if (ev & PM_LLAV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (power6_marked_instr_event(event[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) mmcra |= MMCRA_SAMPLE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (pmc < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mmcr->mmcr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (pmc_inuse & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) mmcr->mmcr0 = MMCR0_PMC1CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (pmc_inuse & 0xe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mmcr->mmcr0 |= MMCR0_PMCjCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mmcr->mmcr1 = mmcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) mmcr->mmcra = mmcra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * Layout of constraint bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * 0-1 add field: number of uses of PMC1 (max 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * 2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * 12-15 add field: number of uses of PMC1-4 (max 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * 16-19 select field: unit on byte 0 of event bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * 32-34 select field: nest (subunit) event selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int p6_get_constraint(u64 event, unsigned long *maskp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int pmc, byte, sh, subunit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned long mask = 0, value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) sh = (pmc - 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mask |= 2 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) value |= 1 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (event & PM_BUSEVENT_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) sh = byte * 4 + (16 - PM_UNIT_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mask |= PM_UNIT_MSKS << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) mask |= (unsigned long)PM_SUBUNIT_MSK << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) value |= (unsigned long)subunit << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (pmc <= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) mask |= 0x8000; /* add field for count of PMC1-4 uses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) value |= 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *maskp = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *valp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int p6_limited_pmc_event(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return pmc == 5 || pmc == 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define MAX_ALT 4 /* at most 4 alternatives for any event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const unsigned int event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x0130e8, 0x2000f6, 0x3000fc }, /* PM_PTEG_RELOAD_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x080088, 0x200054, 0x3000f0 }, /* PM_ST_MISS_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0x10000a, 0x2000f4, 0x600005 }, /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x10000b, 0x2000f5 }, /* PM_RUN_COUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 0x10000e, 0x400010 }, /* PM_PURR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0x100010, 0x4000f8 }, /* PM_FLUSH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0x10001a, 0x200010 }, /* PM_MRK_INST_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0x100026, 0x3000f8 }, /* PM_TB_BIT_TRANS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 0x100054, 0x2000f0 }, /* PM_ST_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0x100056, 0x2000fc }, /* PM_L1_ICACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0x1000f0, 0x40000a }, /* PM_INST_IMC_MATCH_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 0x1000f8, 0x200008 }, /* PM_GCT_EMPTY_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0x1000fc, 0x400006 }, /* PM_LSU_DERAT_MISS_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 0x20000e, 0x400007 }, /* PM_LSU_DERAT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 0x200012, 0x300012 }, /* PM_INST_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0x2000f2, 0x3000f2 }, /* PM_INST_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 0x2000f8, 0x300010 }, /* PM_EXT_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 0x2000fe, 0x300056 }, /* PM_DATA_FROM_L2MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0x2d0030, 0x30001a }, /* PM_MRK_FPU_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0x30000a, 0x400018 }, /* PM_MRK_INST_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x3000f6, 0x40000e }, /* PM_L1_DCACHE_RELOAD_VALID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 0x3000fe, 0x400056 }, /* PM_DATA_FROM_L3MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * This could be made more efficient with a binary search on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * a presorted list, if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int find_alternatives_list(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) unsigned int alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (event < event_alternatives[i][0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) for (j = 0; j < MAX_ALT; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) alt = event_alternatives[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (!alt || event < alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (event == alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int i, j, nlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) unsigned int psel, pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) unsigned int nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u64 aevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) alt[0] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) nlim = p6_limited_pmc_event(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* check the alternatives table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) i = find_alternatives_list(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* copy out alternatives from list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (j = 0; j < MAX_ALT; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) aevent = event_alternatives[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (!aevent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (aevent != event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) alt[nalt++] = aevent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) nlim += p6_limited_pmc_event(aevent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Check for alternative ways of computing sum events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) psel = event & (PM_PMCSEL_MSK & ~1); /* ignore edge bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (pmc && (psel == 0x32 || psel == 0x34))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ((5 - pmc) << PM_PMC_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (pmc && (psel == 0x38 || psel == 0x3a))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (flags & PPMU_ONLY_COUNT_RUN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * We're only counting in RUN state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * so PM_CYC is equivalent to PM_RUN_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * This doesn't include alternatives that don't provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * any extra flexibility in assigning PMCs (e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Note that even with these additional alternatives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * we never end up with more than 4 alternatives for any event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) j = nalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < nalt; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch (alt[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case 0x1e: /* PM_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) alt[j++] = 0x600005; /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ++nlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case 0x10000a: /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) alt[j++] = 0x1e; /* PM_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case 2: /* PM_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) alt[j++] = 0x500009; /* PM_RUN_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) ++nlim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case 0x500009: /* PM_RUN_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) alt[j++] = 2; /* PM_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case 0x10000e: /* PM_PURR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) alt[j++] = 0x4000f4; /* PM_RUN_PURR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) case 0x4000f4: /* PM_RUN_PURR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) alt[j++] = 0x10000e; /* PM_PURR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) nalt = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* remove the limited PMC events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < nalt; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (!p6_limited_pmc_event(alt[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) alt[j] = alt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ++j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) nalt = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* remove all but the limited PMC events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) for (i = 0; i < nalt; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (p6_limited_pmc_event(alt[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) alt[j] = alt[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ++j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) nalt = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return nalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static void p6_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Set PMCxSEL to 0 to disable PMCx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (pmc <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int power6_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [PERF_COUNT_HW_CPU_CYCLES] = 0x1e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [PERF_COUNT_HW_INSTRUCTIONS] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) [PERF_COUNT_HW_CACHE_REFERENCES] = 0x280030, /* LD_REF_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [PERF_COUNT_HW_CACHE_MISSES] = 0x30000c, /* LD_MISS_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0, /* BR_PRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) [PERF_COUNT_HW_BRANCH_MISSES] = 0x400052, /* BR_MPRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) [C(OP_READ)] = { 0x280030, 0x80080 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) [C(OP_WRITE)] = { 0x180032, 0x80088 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) [C(OP_PREFETCH)] = { 0x810a4, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) [C(OP_READ)] = { 0, 0x100056 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) [C(OP_PREFETCH)] = { 0x4008c, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) [C(OP_READ)] = { 0x150730, 0x250532 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) [C(OP_WRITE)] = { 0x250432, 0x150432 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) [C(OP_PREFETCH)] = { 0x810a6, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) [C(OP_READ)] = { 0, 0x20000e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) [C(OP_READ)] = { 0, 0x420ce },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) [C(OP_READ)] = { 0x430e6, 0x400052 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) [C(OP_READ)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct power_pmu power6_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .name = "POWER6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .n_counter = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .max_alternatives = MAX_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .add_fields = 0x1555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .test_adder = 0x3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .compute_mmcr = p6_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .get_constraint = p6_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .get_alternatives = p6_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .disable_pmc = p6_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .limited_pmc_event = p6_limited_pmc_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .n_generic = ARRAY_SIZE(power6_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .generic_events = power6_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .cache_events = &power6_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int init_power6_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power6"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return register_power_pmu(&power6_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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