^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for POWER5 (not POWER5++) processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Bits in event code for POWER5 (not POWER5++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PM_PMC_SH 20 /* PMC number (1-based) for direct events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM_PMC_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM_UNIT_SH 16 /* TTMMUX number and setting - unit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM_UNIT_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PM_BYTE_SH 12 /* Byte number of event bus to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PM_BYTE_MSK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PM_GRS_SH 8 /* Storage subsystem mux select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PM_GRS_MSK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PM_BUSEVENT_MSK 0x80 /* Set if event uses event bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PM_PMCSEL_MSK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Values in PM_UNIT field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PM_FPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PM_ISU0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PM_IFU 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PM_ISU1 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PM_IDU 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PM_ISU0_ALT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM_GRS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PM_LSU0 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PM_LSU1 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PM_LASTUNIT 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Bits in MMCR1 for POWER5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MMCR1_TTM0SEL_SH 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MMCR1_TTM1SEL_SH 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MMCR1_TTM2SEL_SH 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MMCR1_TTM3SEL_SH 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MMCR1_TTMSEL_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MMCR1_TD_CP_DBG0SEL_SH 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MMCR1_TD_CP_DBG1SEL_SH 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MMCR1_TD_CP_DBG2SEL_SH 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MMCR1_TD_CP_DBG3SEL_SH 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MMCR1_GRS_L2SEL_SH 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MMCR1_GRS_L2SEL_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MMCR1_GRS_L3SEL_SH 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MMCR1_GRS_L3SEL_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MMCR1_GRS_MCSEL_SH 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MMCR1_GRS_MCSEL_MSK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MMCR1_GRS_FABSEL_SH 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MMCR1_GRS_FABSEL_MSK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MMCR1_PMC1_ADDER_SEL_SH 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MMCR1_PMC2_ADDER_SEL_SH 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MMCR1_PMC3_ADDER_SEL_SH 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MMCR1_PMC4_ADDER_SEL_SH 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MMCR1_PMC1SEL_SH 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MMCR1_PMC2SEL_SH 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MMCR1_PMC3SEL_SH 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MMCR1_PMC4SEL_SH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MMCR1_PMCSEL_MSK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Layout of constraint bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * 6666555555555544444444443333333333222222222211111111110000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * 3210987654321098765432109876543210987654321098765432109876543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * <><>[ ><><>< ><> [ >[ >[ >< >< >< >< ><><><><><><>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * T0T1 NC G0G1G2 G3 UC PS1PS2 B0 B1 B2 B3 P6P5P4P3P2P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * T0 - TTM0 constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * 54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * T1 - TTM1 constraint
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * 52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * NC - number of counters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * 51: NC error 0x0008_0000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * 48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * G0..G3 - GRS mux constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * 46-47: GRS_L2SEL value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * 44-45: GRS_L3SEL value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * 41-44: GRS_MCSEL value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * 39-40: GRS_FABSEL value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * Note that these match up with their bit positions in MMCR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * 37: UC3 error 0x20_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * 36: FPU|IFU|ISU1 events needed 0x10_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * 35: ISU0 events needed 0x08_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 34: IDU|GRS events needed 0x04_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * PS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * 33: PS1 error 0x2_0000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * 31-32: count of events needing PMC1/2 0x1_8000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * PS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * 30: PS2 error 0x4000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * 28-29: count of events needing PMC3/4 0x3000_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * 24-27: Byte 0 event source 0x0f00_0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Encoding as for the event code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * B1, B2, B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * 20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * P1..P6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * 0-11: Count of events needing PMC1..PMC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const int grsel_shift[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Masks and values for using events from the various units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) [PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) [PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int power5_get_constraint(u64 event, unsigned long *maskp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned long *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int pmc, byte, unit, sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int bit, fmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned long mask = 0, value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int grp = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (pmc > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) sh = (pmc - 1) * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) mask |= 2 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) value |= 1 << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (pmc <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) grp = (pmc - 1) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) else if (event != 0x500009 && event != 0x600005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (event & PM_BUSEVENT_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (unit > PM_LASTUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (unit == PM_ISU0_ALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unit = PM_ISU0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mask |= unit_cons[unit][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) value |= unit_cons[unit][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (byte >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (unit != PM_LSU1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ++unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) byte &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (unit == PM_GRS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bit = event & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fmask = (bit == 6)? 7: 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sh = grsel_shift[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) mask |= (unsigned long)fmask << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) << sh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * Bus events on bytes 0 and 2 can be counted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * on PMC1/2; bytes 1 and 3 on PMC3/4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) grp = byte & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Set byte lane select field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) mask |= 0xfUL << (24 - 4 * byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) value |= (unsigned long)unit << (24 - 4 * byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (grp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* increment PMC1/2 field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) mask |= 0x200000000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) value |= 0x080000000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } else if (grp == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* increment PMC3/4 field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mask |= 0x40000000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) value |= 0x10000000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (pmc < 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* need a counter from PMC1-4 set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask |= 0x8000000000000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) value |= 0x1000000000000ul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) *maskp = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) *valp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MAX_ALT 3 /* at most 3 alternatives for any event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static const unsigned int event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x120e4, 0x400002 }, /* PM_GRP_DISP_REJECT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x410c7, 0x441084 }, /* PM_THRD_L2MISS_BOTH_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x100005, 0x600005 }, /* PM_RUN_CYC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x100009, 0x200009, 0x500009 }, /* PM_INST_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x300009, 0x400009 }, /* PM_INST_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * Scan the alternatives table for a match and return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * index into the alternatives table if found, else -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static int find_alternative(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (event < event_alternatives[i][0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (event == event_alternatives[i][j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const unsigned char bytedecode_alternatives[4][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * Some direct events for decodes of event bus byte 3 have alternative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * PMCSEL values on other counters. This returns the alternative
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * event code for those that do, or -1 otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static s64 find_alternative_bdecode(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int pmc, altpmc, pp, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (pmc == 0 || pmc > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) altpmc = 5 - pmc; /* 1 <-> 4, 2 <-> 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) pp = event & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (j = 0; j < 4; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (bytedecode_alternatives[pmc - 1][j] == pp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (altpmc << PM_PMC_SH) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) bytedecode_alternatives[altpmc - 1][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int power5_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) int i, j, nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) s64 ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) alt[0] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) i = find_alternative(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) for (j = 0; j < MAX_ALT; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ae = event_alternatives[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (ae && ae != event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) alt[nalt++] = ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ae = find_alternative_bdecode(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ae > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) alt[nalt++] = ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return nalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * Map of which direct events on which PMCs are marked instruction events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * Bit 0 is set if it is marked for all PMCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * The 0x80 bit indicates a byte decode PMCSEL value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static unsigned char direct_event_is_marked[0x28] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 0, /* 00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x1f, /* 01 PM_IOPS_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 0x2, /* 02 PM_MRK_GRP_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0xe, /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0, /* 04 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 0x1c, /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 0x80, /* 06 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 0x80, /* 07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0, 0, 0,/* 08 - 0a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 0x18, /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0, /* 0c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 0x80, /* 0d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x80, /* 0e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0, /* 0f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0, /* 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x14, /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 0, /* 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x10, /* 13 PM_MRK_GRP_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 0x1f, /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x2, /* 15 PM_MRK_GRP_ISSUED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x80, /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x80, /* 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 0x80, /* 1d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x80, /* 1e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0, /* 1f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 0x80, /* 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x80, /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x80, /* 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x80, /* 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x80, /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x80, /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x80, /* 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x80, /* 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Returns 1 if event counts things relating to marked instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static int power5_marked_instr_event(u64 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int pmc, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int bit, byte, unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) psel = event & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (pmc >= 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) bit = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (psel < sizeof(direct_event_is_marked)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (direct_event_is_marked[psel] & (1 << pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (direct_event_is_marked[psel] & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) bit = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) else if (psel == 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) bit = pmc - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) else if (psel == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) bit = 4 - pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) else if (psel == 0x1b && (pmc == 1 || pmc == 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) bit = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) } else if ((psel & 0x58) == 0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) bit = psel & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (!(event & PM_BUSEVENT_MSK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (unit == PM_LSU0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) mask = 0x5dff00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) } else if (unit == PM_LSU1 && byte >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) byte -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mask = 0x5f00c0aa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return (mask >> (byte * 8 + bit)) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int power5_compute_mmcr(u64 event[], int n_ev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int hwc[], struct mmcr_regs *mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct perf_event *pevents[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned long mmcr1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int pmc, unit, byte, psel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int ttm, grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int i, isbus, bit, grsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int pmc_inuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int pmc_grp_use[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned char busbyte[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) unsigned char unituse[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ttmuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (n_ev > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* First pass to count resource use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pmc_grp_use[0] = pmc_grp_use[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) memset(busbyte, 0, sizeof(busbyte));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) memset(unituse, 0, sizeof(unituse));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (pmc > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (pmc_inuse & (1 << (pmc - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pmc_inuse |= 1 << (pmc - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* count 1/2 vs 3/4 use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (pmc <= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ++pmc_grp_use[(pmc - 1) >> 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (event[i] & PM_BUSEVENT_MSK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (unit > PM_LASTUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (unit == PM_ISU0_ALT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unit = PM_ISU0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (byte >= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (unit != PM_LSU1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ++unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) byte &= 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (!pmc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ++pmc_grp_use[byte & 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (busbyte[byte] && busbyte[byte] != unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) busbyte[byte] = unit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unituse[unit] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Assign resources and set multiplexer selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * choice we have to deal with.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (unituse[PM_ISU0] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unituse[PM_ISU0_ALT] = 1; /* move ISU to TTM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unituse[PM_ISU0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Set TTM[01]SEL fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ttmuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) for (i = PM_FPU; i <= PM_ISU1; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!unituse[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (ttmuse++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ttmuse = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) for (; i <= PM_GRS; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!unituse[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ttmuse++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ttmuse > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (byte = 0; byte < 4; ++byte) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) unit = busbyte[byte];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (!unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* get ISU0 through TTM1 rather than TTM0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unit = PM_ISU0_ALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) } else if (unit == PM_LSU1 + 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* select lower word of LSU1 for this byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ttm = unit >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) mmcr1 |= (unsigned long)ttm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) psel = event[i] & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) isbus = event[i] & PM_BUSEVENT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (!pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Bus event or any-PMC direct event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) for (pmc = 0; pmc < 4; ++pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (pmc_inuse & (1 << pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) grp = (pmc >> 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (isbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (grp == (byte & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) } else if (pmc_grp_use[grp] < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ++pmc_grp_use[grp];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) pmc_inuse |= 1 << pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) } else if (pmc <= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Direct event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) --pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* add events on higher-numbered bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Instructions or run cycles on PMC5/6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) --pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (isbus && unit == PM_GRS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bit = psel & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (power5_marked_instr_event(event[i]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mmcra |= MMCRA_SAMPLE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (pmc <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) hwc[i] = pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Return MMCRx values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) mmcr->mmcr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (pmc_inuse & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) mmcr->mmcr0 = MMCR0_PMC1CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (pmc_inuse & 0x3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mmcr->mmcr0 |= MMCR0_PMCjCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mmcr->mmcr1 = mmcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mmcr->mmcra = mmcra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void power5_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (pmc <= 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mmcr->mmcr1 &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static int power5_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) [PERF_COUNT_HW_CPU_CYCLES] = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) [PERF_COUNT_HW_INSTRUCTIONS] = 0x100009,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) [PERF_COUNT_HW_CACHE_REFERENCES] = 0x4c1090, /* LD_REF_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) [PERF_COUNT_HW_CACHE_MISSES] = 0x3c1088, /* LD_MISS_L1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4, /* BR_ISSUED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) [PERF_COUNT_HW_BRANCH_MISSES] = 0x230e5, /* BR_MPRED_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) [C(OP_READ)] = { 0x4c1090, 0x3c1088 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) [C(OP_WRITE)] = { 0x3c1090, 0xc10c3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) [C(OP_PREFETCH)] = { 0xc70e7, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) [C(OP_READ)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) [C(OP_PREFETCH)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) [C(OP_READ)] = { 0, 0x3c309b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) [C(OP_WRITE)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) [C(OP_PREFETCH)] = { 0xc50c3, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) [C(OP_READ)] = { 0x2c4090, 0x800c4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) [C(ITLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) [C(OP_READ)] = { 0, 0x800c0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) [C(OP_READ)] = { 0x230e4, 0x230e5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) [C(OP_READ)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static struct power_pmu power5_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .name = "POWER5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .n_counter = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .max_alternatives = MAX_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .add_fields = 0x7000090000555ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .test_adder = 0x3000490000000ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .compute_mmcr = power5_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .get_constraint = power5_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .get_alternatives = power5_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .disable_pmc = power5_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .n_generic = ARRAY_SIZE(power5_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .generic_events = power5_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .cache_events = &power5_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .flags = PPMU_HAS_SSLOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int init_power5_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power5"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return register_power_pmu(&power5_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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