^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for POWER10 processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2020 Athira Rajeev, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) "power10-pmu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include "isa207-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Raw event encoding for Power10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * 60 56 52 48 44 40 36 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | | [ ] [ src_match ] [ src_mask ] | [ ] [ l2l3_sel ] [ thresh_ctl ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * | | *- IFM (Linux) | | thresh start/stop -*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * | *- BHRB (Linux) | src_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * *- EBB (Linux) *invert_bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * 28 24 20 16 12 8 4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * [ ] [ sample ] [ ] [ ] [ pmc ] [unit ] [ ] | m [ pmcxsel ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * | | | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * | | | | | | *- mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * | | | *- L1/L2/L3 cache_sel | |*-radix_scope_qual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * | | sdar_mode |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * | *- sampling mode for marked events *- combine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * *- thresh_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Below uses IBM bit numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * MMCR1[x:y] = unit (PMCxUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * MMCR1[24] = pmc1combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * MMCR1[25] = pmc1combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * MMCR1[26] = pmc2combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * MMCR1[27] = pmc2combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * MMCR1[28] = pmc3combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * MMCR1[29] = pmc3combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * MMCR1[30] = pmc4combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * MMCR1[31] = pmc4combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * MMCR1[20:27] = thresh_ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * MMCR1[20:27] = thresh_ctl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * MMCRA[48:55] = thresh_ctl (THRESH START/END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * if thresh_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * MMCRA[45:47] = thresh_sel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * if l2l3_sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * MMCR2[56:60] = l2l3_sel[0:4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * MMCR1[16] = cache_sel[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * MMCR1[17] = cache_sel[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * MMCR1[18] = radix_scope_qual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * if mark:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * MMCRA[63] = 1 (SAMPLE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * MMCRA[57:59] = sample[0:2] (RAND_SAMP_ELIG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * MMCRA[61:62] = sample[3:4] (RAND_SAMP_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * if EBB and BHRB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * MMCRA[32:33] = IFM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * MMCRA[SDAR_MODE] = sdar_mode[0:1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Some power10 event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EVENT(_name, _code) enum{_name = _code}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include "power10-events-list.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* MMCRA IFM bits - POWER10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define POWER10_MMCRA_IFM1 0x0000000040000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define POWER10_MMCRA_IFM2 0x0000000080000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define POWER10_MMCRA_IFM3 0x00000000C0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define POWER10_MMCRA_BHRB_MASK 0x00000000C0000000UL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) extern u64 PERF_REG_EXTENDED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Table of alternatives, sorted by column 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const unsigned int power10_event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { PM_RUN_CYC_ALT, PM_RUN_CYC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { PM_RUN_INST_CMPL_ALT, PM_RUN_INST_CMPL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int num_alt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) num_alt = isa207_get_alternatives(event, alt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ARRAY_SIZE(power10_event_alternatives), flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) power10_event_alternatives);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return num_alt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) GENERIC_EVENT_ATTR(cpu-cycles, PM_RUN_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) GENERIC_EVENT_ATTR(instructions, PM_RUN_INST_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) GENERIC_EVENT_ATTR(branch-instructions, PM_BR_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) GENERIC_EVENT_ATTR(branch-misses, PM_BR_MPRED_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GENERIC_EVENT_ATTR(cache-references, PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) GENERIC_EVENT_ATTR(cache-misses, PM_LD_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) GENERIC_EVENT_ATTR(mem-loads, MEM_LOADS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) GENERIC_EVENT_ATTR(mem-stores, MEM_STORES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_LD_PREFETCH_CACHE_LINE_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) CACHE_EVENT_ATTR(LLC-load-misses, PM_DATA_FROM_L3MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) CACHE_EVENT_ATTR(LLC-loads, PM_DATA_FROM_L3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) CACHE_EVENT_ATTR(branch-load-misses, PM_BR_MPRED_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CACHE_EVENT_ATTR(branch-loads, PM_BR_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CACHE_EVENT_ATTR(dTLB-load-misses, PM_DTLB_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) CACHE_EVENT_ATTR(iTLB-load-misses, PM_ITLB_MISS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static struct attribute *power10_events_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) GENERIC_EVENT_PTR(PM_RUN_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) GENERIC_EVENT_PTR(PM_RUN_INST_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) GENERIC_EVENT_PTR(PM_BR_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) GENERIC_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) GENERIC_EVENT_PTR(PM_LD_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) GENERIC_EVENT_PTR(MEM_LOADS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) GENERIC_EVENT_PTR(MEM_STORES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CACHE_EVENT_PTR(PM_LD_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CACHE_EVENT_PTR(PM_LD_REF_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CACHE_EVENT_PTR(PM_ST_MISS_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CACHE_EVENT_PTR(PM_INST_FROM_L1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CACHE_EVENT_PTR(PM_IC_PREF_REQ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CACHE_EVENT_PTR(PM_DATA_FROM_L3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CACHE_EVENT_PTR(PM_BR_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CACHE_EVENT_PTR(PM_DTLB_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CACHE_EVENT_PTR(PM_ITLB_MISS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static struct attribute_group power10_pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .attrs = power10_events_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) PMU_FORMAT_ATTR(event, "config:0-59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) PMU_FORMAT_ATTR(mark, "config:8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) PMU_FORMAT_ATTR(combine, "config:10-11");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) PMU_FORMAT_ATTR(unit, "config:12-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) PMU_FORMAT_ATTR(pmc, "config:16-19");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) PMU_FORMAT_ATTR(cache_sel, "config:20-21");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) PMU_FORMAT_ATTR(sdar_mode, "config:22-23");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) PMU_FORMAT_ATTR(sample_mode, "config:24-28");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) PMU_FORMAT_ATTR(thresh_sel, "config:29-31");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) PMU_FORMAT_ATTR(thresh_stop, "config:32-35");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) PMU_FORMAT_ATTR(thresh_start, "config:36-39");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) PMU_FORMAT_ATTR(l2l3_sel, "config:40-44");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) PMU_FORMAT_ATTR(src_sel, "config:45-46");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) PMU_FORMAT_ATTR(invert_bit, "config:47");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) PMU_FORMAT_ATTR(src_mask, "config:48-53");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) PMU_FORMAT_ATTR(src_match, "config:54-59");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) PMU_FORMAT_ATTR(radix_scope, "config:9");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static struct attribute *power10_pmu_format_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) &format_attr_pmcxsel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) &format_attr_mark.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) &format_attr_combine.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) &format_attr_unit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) &format_attr_pmc.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) &format_attr_cache_sel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) &format_attr_sdar_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) &format_attr_sample_mode.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) &format_attr_thresh_sel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) &format_attr_thresh_stop.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) &format_attr_thresh_start.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) &format_attr_l2l3_sel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) &format_attr_src_sel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) &format_attr_invert_bit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) &format_attr_src_mask.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) &format_attr_src_match.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) &format_attr_radix_scope.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static struct attribute_group power10_pmu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .attrs = power10_pmu_format_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const struct attribute_group *power10_pmu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) &power10_pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) &power10_pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static int power10_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [PERF_COUNT_HW_CPU_CYCLES] = PM_RUN_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) [PERF_COUNT_HW_INSTRUCTIONS] = PM_RUN_INST_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static u64 power10_bhrb_filter_map(u64 branch_sample_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u64 pmu_bhrb_filter = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* BHRB and regular PMU events share the same privilege state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * filter configuration. BHRB is always recorded along with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * regular PMU event. As the privilege state filter is handled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * in the basic PMC configuration of the accompanying regular
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * PMU event, we ignore any separate BHRB specific request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* No branch filter requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Invalid branch filter options - HW does not support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) pmu_bhrb_filter |= POWER10_MMCRA_IFM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) pmu_bhrb_filter |= POWER10_MMCRA_IFM3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pmu_bhrb_filter |= POWER10_MMCRA_IFM1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return pmu_bhrb_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Every thing else is unsupported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void power10_config_bhrb(u64 pmu_bhrb_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Enable BHRB filter in PMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [C(L1D)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [C(RESULT_ACCESS)] = PM_LD_REF_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) [C(RESULT_MISS)] = PM_LD_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [C(RESULT_ACCESS)] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) [C(RESULT_MISS)] = PM_ST_MISS_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) [C(RESULT_MISS)] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) [C(L1I)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) [C(RESULT_MISS)] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) [C(LL)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) [C(RESULT_MISS)] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) [C(DTLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) [C(RESULT_ACCESS)] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) [C(RESULT_MISS)] = PM_DTLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) [C(ITLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) [C(RESULT_ACCESS)] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [C(RESULT_MISS)] = PM_ITLB_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) [C(BPU)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) [C(RESULT_ACCESS)] = PM_BR_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) [C(NODE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) [C(OP_READ)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) [C(OP_WRITE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) [C(OP_PREFETCH)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) [C(RESULT_ACCESS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) [C(RESULT_MISS)] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #undef C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static struct power_pmu power10_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .name = "POWER10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .n_counter = MAX_PMU_COUNTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .add_fields = ISA207_ADD_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .test_adder = ISA207_TEST_ADDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .group_constraint_mask = CNST_CACHE_PMC4_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .group_constraint_val = CNST_CACHE_PMC4_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .compute_mmcr = isa207_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .config_bhrb = power10_config_bhrb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .bhrb_filter_map = power10_bhrb_filter_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .get_constraint = isa207_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .get_alternatives = power10_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .get_mem_data_src = isa207_get_mem_data_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .get_mem_weight = isa207_get_mem_weight,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .disable_pmc = isa207_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .flags = PPMU_HAS_SIER | PPMU_ARCH_207S |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PPMU_ARCH_31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .n_generic = ARRAY_SIZE(power10_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .generic_events = power10_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .cache_events = &power10_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .attr_groups = power10_pmu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .bhrb_nr = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .capabilities = PERF_PMU_CAP_EXTENDED_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int init_power10_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Comes from cpu_specs[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power10"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /* Set the PERF_REG_EXTENDED_MASK here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) rc = register_power_pmu(&power10_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Tell userspace that EBB is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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