Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Performance counter support for MPC7450-family processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define N_COUNTER	6	/* Number of hardware counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define MAX_ALT		3	/* Maximum number of event alternative codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * Bits in event code for MPC7450 family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PM_THRMULT_MSKS	0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PM_THRESH_SH	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PM_THRESH_MSK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PM_PMC_SH	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define PM_PMC_MSK	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PM_PMCSEL_MSK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * Classify events according to how specific their PMC requirements are.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Result is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *	0: can go on any PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *	1: can go on PMCs 1-4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *	2: can go on PMCs 1,2,4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *	3: can go on PMCs 1 or 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *	4: can only go on one PMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *	-1: event code is invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define N_CLASSES	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) static int mpc7450_classify_event(u32 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	int pmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		if (pmc > N_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	event &= PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	if (event <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (event <= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (event <= 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (event <= 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * Events using threshold and possible threshold scale:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  *	code	scale?	name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  *	11e	N	PM_INSTQ_EXCEED_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  *	11f	N	PM_ALTV_IQ_EXCEED_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *	128	Y	PM_DTLB_SEARCH_EXCEED_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  *	12b	Y	PM_LD_MISS_EXCEED_L1_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  *	220	N	PM_CQ_EXCEED_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  *	30c	N	PM_GPR_RB_EXCEED_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  *	30d	?	PM_FPR_IQ_EXCEED_CYC ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *	311	Y	PM_ITLB_SEARCH_EXCEED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  *	410	N	PM_GPR_IQ_EXCEED_CYC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * Return use of threshold and threshold scale bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  * 0 = uses neither, 1 = uses threshold, 2 = uses both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int mpc7450_threshold_use(u32 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int pmc, sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	sel = event & PM_PMCSEL_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	switch (pmc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		if (sel == 0x1e || sel == 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		if (sel == 0x28 || sel == 0x2b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		if (sel == 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		if (sel == 0xc || sel == 0xd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		if (sel == 0x11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		if (sel == 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)  * Layout of constraint bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * 33222222222211111111110000000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * 10987654321098765432109876543210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  *  |<    ><  > < > < ><><><><><><>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)  *  TS TV   G4   G3  G2P6P5P4P3P2P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * P1 - P6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  *	0 - 11: Count of events needing PMC1 .. PMC6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * G2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  *	12 - 14: Count of events needing PMC1 or PMC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * G3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  *	16 - 18: Count of events needing PMC1, PMC2 or PMC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  * G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  *	20 - 23: Count of events needing PMC1, PMC2, PMC3 or PMC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)  * TV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)  *	24 - 29: Threshold value requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)  * TS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *	30: Threshold scale value requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static u32 pmcbits[N_COUNTER][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ 0x00844002, 0x00111001 },	/* PMC1 mask, value: P1,G2,G3,G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{ 0x00844008, 0x00111004 },	/* PMC2: P2,G2,G3,G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{ 0x00800020, 0x00100010 },	/* PMC3: P3,G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{ 0x00840080, 0x00110040 },	/* PMC4: P4,G3,G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ 0x00000200, 0x00000100 },	/* PMC5: P5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ 0x00000800, 0x00000400 }	/* PMC6: P6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static u32 classbits[N_CLASSES - 1][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	{ 0x00000000, 0x00000000 },	/* class 0: no constraint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{ 0x00800000, 0x00100000 },	/* class 1: G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	{ 0x00040000, 0x00010000 },	/* class 2: G3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	{ 0x00004000, 0x00001000 },	/* class 3: G2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int mpc7450_get_constraint(u64 event, unsigned long *maskp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				  unsigned long *valp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	int pmc, class;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u32 mask, value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int thresh, tuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	class = mpc7450_classify_event(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (class < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (class == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		pmc = ((unsigned int)event >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		mask  = pmcbits[pmc - 1][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		value = pmcbits[pmc - 1][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		mask  = classbits[class][0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		value = classbits[class][1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	tuse = mpc7450_threshold_use(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	if (tuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		thresh = ((unsigned int)event >> PM_THRESH_SH) & PM_THRESH_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		mask  |= 0x3f << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		value |= thresh << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		if (tuse == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			mask |= 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			if ((unsigned int)event & PM_THRMULT_MSKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 				value |= 0x40000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	*maskp = mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	*valp = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const unsigned int event_alternatives[][MAX_ALT] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	{ 0x217, 0x317 },		/* PM_L1_DCACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	{ 0x418, 0x50f, 0x60f },	/* PM_SNOOP_RETRY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	{ 0x502, 0x602 },		/* PM_L2_HIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	{ 0x503, 0x603 },		/* PM_L3_HIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	{ 0x504, 0x604 },		/* PM_L2_ICACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	{ 0x505, 0x605 },		/* PM_L3_ICACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	{ 0x506, 0x606 },		/* PM_L2_DCACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	{ 0x507, 0x607 },		/* PM_L3_DCACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	{ 0x50a, 0x623 },		/* PM_LD_HIT_L3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	{ 0x50b, 0x624 },		/* PM_ST_HIT_L3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	{ 0x50d, 0x60d },		/* PM_L2_TOUCH_HIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	{ 0x50e, 0x60e },		/* PM_L3_TOUCH_HIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	{ 0x512, 0x612 },		/* PM_INT_LOCAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	{ 0x513, 0x61d },		/* PM_L2_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ 0x514, 0x61e },		/* PM_L3_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)  * Scan the alternatives table for a match and return the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)  * index into the alternatives table if found, else -1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int find_alternative(u32 event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		if (event < event_alternatives[i][0])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			if (event == event_alternatives[i][j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 				return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int mpc7450_get_alternatives(u64 event, unsigned int flags, u64 alt[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int i, j, nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u32 ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	alt[0] = event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	nalt = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	i = find_alternative((u32)event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	if (i >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		for (j = 0; j < MAX_ALT; ++j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 			ae = event_alternatives[i][j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 			if (ae && ae != (u32)event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 				alt[nalt++] = ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return nalt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)  * Bitmaps of which PMCs each class can use for classes 0 - 3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)  * Bit i is set if PMC i+1 is usable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static const u8 classmap[N_CLASSES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	0x3f, 0x0f, 0x0b, 0x03, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Bit position and width of each PMCSEL field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const int pmcsel_shift[N_COUNTER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	6,	0,	27,	22,	17,	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const u32 pmcsel_mask[N_COUNTER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	0x7f,	0x3f,	0x1f,	0x1f,	0x1f,	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  * Compute MMCR0/1/2 values for a set of events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int mpc7450_compute_mmcr(u64 event[], int n_ev, unsigned int hwc[],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 				struct mmcr_regs *mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 				struct perf_event *pevents[])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	u8 event_index[N_CLASSES][N_COUNTER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	int n_classevent[N_CLASSES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	int i, j, class, tuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u32 pmc_inuse = 0, pmc_avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	u32 mmcr0 = 0, mmcr1 = 0, mmcr2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	u32 ev, pmc, thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	if (n_ev > N_COUNTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	/* First pass: count usage in each class */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	for (i = 0; i < N_CLASSES; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		n_classevent[i] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	for (i = 0; i < n_ev; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		class = mpc7450_classify_event(event[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		if (class < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		j = n_classevent[class]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		event_index[class][j] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	/* Second pass: allocate PMCs from most specific event to least */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	for (class = N_CLASSES - 1; class >= 0; --class) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		for (i = 0; i < n_classevent[class]; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 			ev = event[event_index[class][i]];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			if (class == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 				pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 				if (pmc_inuse & (1 << (pmc - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 					return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 				/* Find a suitable PMC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 				pmc_avail = classmap[class] & ~pmc_inuse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				if (!pmc_avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 					return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				pmc = ffs(pmc_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			pmc_inuse |= 1 << (pmc - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			tuse = mpc7450_threshold_use(ev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			if (tuse) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				thresh = (ev >> PM_THRESH_SH) & PM_THRESH_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 				mmcr0 |= thresh << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				if (tuse == 2 && (ev & PM_THRMULT_MSKS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 					mmcr2 = 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			ev &= pmcsel_mask[pmc - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			ev <<= pmcsel_shift[pmc - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			if (pmc <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				mmcr0 |= ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				mmcr1 |= ev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			hwc[event_index[class][i]] = pmc - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (pmc_inuse & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		mmcr0 |= MMCR0_PMC1CE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (pmc_inuse & 0x3e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		mmcr0 |= MMCR0_PMCnCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	/* Return MMCRx values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	mmcr->mmcr0 = mmcr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	mmcr->mmcr1 = mmcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mmcr->mmcr2 = mmcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	 * 32-bit doesn't have an MMCRA and uses SPRN_MMCR2 to define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	 * SPRN_MMCRA. So assign mmcra of cpu_hw_events with `mmcr2`
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	 * value to ensure that any write to this SPRN_MMCRA will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	 * use mmcr2 value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mmcr->mmcra = mmcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)  * Disable counting by a PMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)  * Note that the pmc argument is 0-based here, not 1-based.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void mpc7450_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (pmc <= 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		mmcr->mmcr0 &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		mmcr->mmcr1 &= ~(pmcsel_mask[pmc] << pmcsel_shift[pmc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int mpc7450_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	[PERF_COUNT_HW_CPU_CYCLES]		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	[PERF_COUNT_HW_INSTRUCTIONS]		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	[PERF_COUNT_HW_CACHE_MISSES]		= 0x217, /* PM_L1_DCACHE_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	[PERF_COUNT_HW_BRANCH_INSTRUCTIONS]	= 0x122, /* PM_BR_CMPL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	[PERF_COUNT_HW_BRANCH_MISSES] 		= 0x41c, /* PM_BR_MPRED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define C(x)	PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)  * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)  * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)  * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static u64 mpc7450_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	[C(L1D)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		[C(OP_READ)] = {	0,		0x225	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		[C(OP_WRITE)] = {	0,		0x227	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		[C(OP_PREFETCH)] = {	0,		0	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	[C(L1I)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		[C(OP_READ)] = {	0x129,		0x115	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		[C(OP_WRITE)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		[C(OP_PREFETCH)] = {	0x634,		0	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	[C(LL)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		[C(OP_READ)] = {	0,		0	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		[C(OP_WRITE)] = {	0,		0	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		[C(OP_PREFETCH)] = {	0,		0	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	[C(DTLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		[C(OP_READ)] = {	0,		0x312	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		[C(OP_WRITE)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		[C(OP_PREFETCH)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	[C(ITLB)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		[C(OP_READ)] = {	0,		0x223	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		[C(OP_WRITE)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		[C(OP_PREFETCH)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	[C(BPU)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		[C(OP_READ)] = {	0x122,		0x41c	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		[C(OP_WRITE)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		[C(OP_PREFETCH)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	[C(NODE)] = {		/* 	RESULT_ACCESS	RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		[C(OP_READ)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		[C(OP_WRITE)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		[C(OP_PREFETCH)] = {	-1,		-1	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct power_pmu mpc7450_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.name			= "MPC7450 family",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.n_counter		= N_COUNTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.max_alternatives	= MAX_ALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.add_fields		= 0x00111555ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.test_adder		= 0x00301000ul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.compute_mmcr		= mpc7450_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	.get_constraint		= mpc7450_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.get_alternatives	= mpc7450_get_alternatives,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.disable_pmc		= mpc7450_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	.n_generic		= ARRAY_SIZE(mpc7450_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.generic_events		= mpc7450_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.cache_events		= &mpc7450_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int __init init_mpc7450_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	    strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/7450"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	return register_power_pmu(&mpc7450_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) early_initcall(init_mpc7450_pmu);