^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2013 Michael Ellerman, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _LINUX_POWERPC_PERF_ISA207_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _LINUX_POWERPC_PERF_ISA207_COMMON_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EVENT_EBB_MASK 1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EVENT_EBB_SHIFT PERF_EVENT_CONFIG_EBB_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EVENT_BHRB_MASK 1ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EVENT_BHRB_SHIFT 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EVENT_WANTS_BHRB (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EVENT_IFM_MASK 3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EVENT_IFM_SHIFT 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EVENT_THR_CMP_SHIFT 40 /* Threshold CMP value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EVENT_THR_CMP_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EVENT_THR_CTL_SHIFT 32 /* Threshold control value (start/stop) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EVENT_THR_CTL_MASK 0xffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EVENT_THR_SEL_SHIFT 29 /* Threshold select value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EVENT_THR_SEL_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EVENT_THRESH_SHIFT 29 /* All threshold bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define EVENT_THRESH_MASK 0x1fffffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define EVENT_SAMPLE_SHIFT 24 /* Sampling mode & eligibility */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define EVENT_SAMPLE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define EVENT_CACHE_SEL_SHIFT 20 /* L2/L3 cache select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EVENT_CACHE_SEL_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define EVENT_IS_L1 (4 << EVENT_CACHE_SEL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define EVENT_PMC_SHIFT 16 /* PMC number (1-based) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EVENT_PMC_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EVENT_UNIT_SHIFT 12 /* Unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EVENT_UNIT_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define EVENT_COMBINE_SHIFT 11 /* Combine bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EVENT_COMBINE_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define EVENT_COMBINE(v) (((v) >> EVENT_COMBINE_SHIFT) & EVENT_COMBINE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define EVENT_MARKED_SHIFT 8 /* Marked bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EVENT_MARKED_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EVENT_IS_MARKED (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EVENT_PSEL_MASK 0xff /* PMCxSEL value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Bits defined by Linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EVENT_LINUX_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ((EVENT_EBB_MASK << EVENT_EBB_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (EVENT_BHRB_MASK << EVENT_BHRB_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) (EVENT_IFM_MASK << EVENT_IFM_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define EVENT_VALID_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ((EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) (EVENT_COMBINE_MASK << EVENT_COMBINE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) EVENT_LINUX_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) EVENT_PSEL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ONLY_PLM \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) (PERF_SAMPLE_BRANCH_USER |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PERF_SAMPLE_BRANCH_KERNEL |\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PERF_SAMPLE_BRANCH_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Contants to support power9 raw encoding format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define p9_EVENT_COMBINE_SHIFT 10 /* Combine bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define p9_EVENT_COMBINE_MASK 0x3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define p9_EVENT_COMBINE(v) (((v) >> p9_EVENT_COMBINE_SHIFT) & p9_EVENT_COMBINE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define p9_SDAR_MODE_SHIFT 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define p9_SDAR_MODE_MASK 0x3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define p9_SDAR_MODE(v) (((v) >> p9_SDAR_MODE_SHIFT) & p9_SDAR_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define p9_EVENT_VALID_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ((p9_SDAR_MODE_MASK << p9_SDAR_MODE_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) (EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EVENT_LINUX_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EVENT_PSEL_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Contants to support power10 raw encoding format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define p10_SDAR_MODE_SHIFT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define p10_SDAR_MODE_MASK 0x3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define p10_SDAR_MODE(v) (((v) >> p10_SDAR_MODE_SHIFT) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) p10_SDAR_MODE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define p10_EVENT_L2L3_SEL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define p10_L2L3_SEL_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define p10_L2L3_EVENT_SHIFT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define p10_EVENT_THRESH_MASK 0xffffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define p10_EVENT_CACHE_SEL_MASK 0x3ull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define p10_EVENT_MMCR3_MASK 0x7fffull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define p10_EVENT_MMCR3_SHIFT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define p10_EVENT_RADIX_SCOPE_QUAL_SHIFT 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define p10_EVENT_RADIX_SCOPE_QUAL_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define p10_MMCR1_RADIX_SCOPE_QUAL_SHIFT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define p10_EVENT_VALID_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ((p10_SDAR_MODE_MASK << p10_SDAR_MODE_SHIFT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) (p10_EVENT_THRESH_MASK << EVENT_THRESH_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (EVENT_SAMPLE_MASK << EVENT_SAMPLE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) (p10_EVENT_CACHE_SEL_MASK << EVENT_CACHE_SEL_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) (EVENT_PMC_MASK << EVENT_PMC_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) (EVENT_UNIT_MASK << EVENT_UNIT_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (p9_EVENT_COMBINE_MASK << p9_EVENT_COMBINE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) (p10_EVENT_MMCR3_MASK << p10_EVENT_MMCR3_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) (EVENT_MARKED_MASK << EVENT_MARKED_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) (p10_EVENT_RADIX_SCOPE_QUAL_MASK << p10_EVENT_RADIX_SCOPE_QUAL_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) EVENT_LINUX_MASK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) EVENT_PSEL_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Layout of constraint bits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * 60 56 52 48 44 40 36 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * [ fab_match ] [ thresh_cmp ] [ thresh_ctl ] [ ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * thresh_sel -*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 28 24 20 16 12 8 4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * [ ] | [ ] | [ sample ] [ ] [6] [5] [4] [3] [2] [1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * | | | | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * BHRB IFM -* | | |*radix_scope | Count of events for each PMC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * EBB -* | | p1, p2, p3, p4, p5, p6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * L1 I/D qualifier -* |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * nc - number of counters -*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * The PMC fields P1..P6, and NC, are adder fields. As we accumulate constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * we want the low bit of each field to be added to any existing value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * Everything else is a value field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CNST_FAB_MATCH_VAL(v) (((v) & EVENT_THR_CTL_MASK) << 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CNST_FAB_MATCH_MASK CNST_FAB_MATCH_VAL(EVENT_THR_CTL_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* We just throw all the threshold bits into the constraint */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CNST_THRESH_VAL(v) (((v) & EVENT_THRESH_MASK) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CNST_THRESH_MASK CNST_THRESH_VAL(EVENT_THRESH_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CNST_THRESH_CTL_SEL_VAL(v) (((v) & 0x7ffull) << 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CNST_THRESH_CTL_SEL_MASK CNST_THRESH_CTL_SEL_VAL(0x7ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CNST_EBB_VAL(v) (((v) & EVENT_EBB_MASK) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CNST_EBB_MASK CNST_EBB_VAL(EVENT_EBB_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CNST_IFM_VAL(v) (((v) & EVENT_IFM_MASK) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CNST_IFM_MASK CNST_IFM_VAL(EVENT_IFM_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CNST_L1_QUAL_VAL(v) (((v) & 3) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CNST_L1_QUAL_MASK CNST_L1_QUAL_VAL(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CNST_SAMPLE_VAL(v) (((v) & EVENT_SAMPLE_MASK) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CNST_SAMPLE_MASK CNST_SAMPLE_VAL(EVENT_SAMPLE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CNST_CACHE_GROUP_VAL(v) (((v) & 0xffull) << 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CNST_CACHE_GROUP_MASK CNST_CACHE_GROUP_VAL(0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CNST_CACHE_PMC4_VAL (1ull << 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CNST_CACHE_PMC4_MASK CNST_CACHE_PMC4_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CNST_L2L3_GROUP_VAL(v) (((v) & 0x1full) << 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CNST_L2L3_GROUP_MASK CNST_L2L3_GROUP_VAL(0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CNST_RADIX_SCOPE_GROUP_VAL(v) (((v) & 0x1ull) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CNST_RADIX_SCOPE_GROUP_MASK CNST_RADIX_SCOPE_GROUP_VAL(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * For NC we are counting up to 4 events. This requires three bits, and we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * the fifth event to overflow and set the 4th bit. To achieve that we bias the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * fields by 3 in test_adder.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CNST_NC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CNST_NC_VAL (1 << CNST_NC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CNST_NC_MASK (8 << CNST_NC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ISA207_TEST_ADDER (3 << CNST_NC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * For the per-PMC fields we have two bits. The low bit is added, so if two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * events ask for the same PMC the sum will overflow, setting the high bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * indicating an error. So our mask sets the high bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CNST_PMC_SHIFT(pmc) ((pmc - 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CNST_PMC_VAL(pmc) (1 << CNST_PMC_SHIFT(pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CNST_PMC_MASK(pmc) (2 << CNST_PMC_SHIFT(pmc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Our add_fields is defined as: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ISA207_ADD_FIELDS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) CNST_PMC_VAL(1) | CNST_PMC_VAL(2) | CNST_PMC_VAL(3) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) CNST_PMC_VAL(4) | CNST_PMC_VAL(5) | CNST_PMC_VAL(6) | CNST_NC_VAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Bits in MMCR1 for PowerISA v2.07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MMCR1_UNIT_SHIFT(pmc) (60 - (4 * ((pmc) - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MMCR1_COMBINE_SHIFT(pmc) (35 - ((pmc) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MMCR1_PMCSEL_SHIFT(pmc) (24 - (((pmc) - 1)) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MMCR1_FAB_SHIFT 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MMCR1_DC_IC_QUAL_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MMCR1_DC_IC_QUAL_SHIFT 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* MMCR1 Combine bits macro for power9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define p9_MMCR1_COMBINE_SHIFT(pmc) (38 - ((pmc - 1) * 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Bits in MMCRA for PowerISA v2.07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MMCRA_SAMP_MODE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MMCRA_SAMP_ELIG_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MMCRA_THR_CTL_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MMCRA_THR_SEL_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MMCRA_THR_CMP_SHIFT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MMCRA_SDAR_MODE_SHIFT 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MMCRA_SDAR_MODE_TLB (1ull << MMCRA_SDAR_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MMCRA_SDAR_MODE_NO_UPDATES ~(0x3ull << MMCRA_SDAR_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MMCRA_SDAR_MODE_DCACHE (2ull << MMCRA_SDAR_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MMCRA_IFM_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MMCRA_THR_CTR_MANT_SHIFT 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MMCRA_THR_CTR_MANT_MASK 0x7Ful
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) MMCRA_THR_CTR_MANT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MMCRA_THR_CTR_EXP_SHIFT 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MMCRA_THR_CTR_EXP_MASK 0x7ul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MMCRA_THR_CTR_EXP(v) (((v) >> MMCRA_THR_CTR_EXP_SHIFT) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MMCRA_THR_CTR_EXP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define P10_MMCRA_THR_CTR_MANT_MASK 0xFFul
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define P10_MMCRA_THR_CTR_MANT(v) (((v) >> MMCRA_THR_CTR_MANT_SHIFT) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) P10_MMCRA_THR_CTR_MANT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* MMCRA Threshold Compare bit constant for power9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define p9_MMCRA_THR_CMP_SHIFT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Bits in MMCR2 for PowerISA v2.07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MMCR2_FCS(pmc) (1ull << (63 - (((pmc) - 1) * 9)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MMCR2_FCP(pmc) (1ull << (62 - (((pmc) - 1) * 9)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MMCR2_FCH(pmc) (1ull << (57 - (((pmc) - 1) * 9)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MAX_ALT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MAX_PMU_COUNTERS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Bits in MMCR3 for PowerISA v3.10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MMCR3_SHIFT(pmc) (49 - (15 * ((pmc) - 1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ISA207_SIER_TYPE_SHIFT 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ISA207_SIER_TYPE_MASK (0x7ull << ISA207_SIER_TYPE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ISA207_SIER_LDST_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ISA207_SIER_LDST_MASK (0x7ull << ISA207_SIER_LDST_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ISA207_SIER_DATA_SRC_SHIFT 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ISA207_SIER_DATA_SRC_MASK (0x7ull << ISA207_SIER_DATA_SRC_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define P(a, b) PERF_MEM_S(a, b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define PH(a, b) (P(LVL, HIT) | P(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define PM(a, b) (P(LVL, MISS) | P(a, b))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int isa207_get_constraint(u64 event, unsigned long *maskp, unsigned long *valp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int isa207_compute_mmcr(u64 event[], int n_ev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int hwc[], struct mmcr_regs *mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct perf_event *pevents[]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void isa207_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int isa207_get_alternatives(u64 event, u64 alt[], int size, unsigned int flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const unsigned int ev_alt[][MAX_ALT]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void isa207_get_mem_data_src(union perf_mem_data_src *dsrc, u32 flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct pt_regs *regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void isa207_get_mem_weight(u64 *weight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags