^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright 2019 Madhavan Srinivasan, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define pr_fmt(fmt) "generic-compat-pmu: " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include "isa207-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Raw event encoding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 60 56 52 48 44 40 36 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 28 24 20 16 12 8 4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * [ pmc ] [unit ] [ ] m [ pmcxsel ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * | |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * | *- mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * *- combine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Below uses IBM bit numbering.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * MMCR1[x:y] = unit (PMCxUNIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * MMCR1[24] = pmc1combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * MMCR1[25] = pmc1combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * MMCR1[26] = pmc2combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * MMCR1[27] = pmc2combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * MMCR1[28] = pmc3combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * MMCR1[29] = pmc3combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * MMCR1[30] = pmc4combine[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * MMCR1[31] = pmc4combine[1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Some power9 event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define EVENT(_name, _code) _name = _code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) EVENT(PM_CYC, 0x0001e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) EVENT(PM_INST_CMPL, 0x00002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #undef EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) GENERIC_EVENT_ATTR(cpu-cycles, PM_CYC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) GENERIC_EVENT_ATTR(instructions, PM_INST_CMPL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static struct attribute *generic_compat_events_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) GENERIC_EVENT_PTR(PM_CYC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GENERIC_EVENT_PTR(PM_INST_CMPL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static struct attribute_group generic_compat_pmu_events_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .name = "events",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .attrs = generic_compat_events_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PMU_FORMAT_ATTR(event, "config:0-19");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PMU_FORMAT_ATTR(mark, "config:8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PMU_FORMAT_ATTR(combine, "config:10-11");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PMU_FORMAT_ATTR(unit, "config:12-15");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PMU_FORMAT_ATTR(pmc, "config:16-19");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static struct attribute *generic_compat_pmu_format_attr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) &format_attr_event.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) &format_attr_pmcxsel.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) &format_attr_mark.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) &format_attr_combine.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) &format_attr_unit.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) &format_attr_pmc.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static struct attribute_group generic_compat_pmu_format_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .name = "format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .attrs = generic_compat_pmu_format_attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static const struct attribute_group *generic_compat_pmu_attr_groups[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) &generic_compat_pmu_format_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) &generic_compat_pmu_events_group,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static int compat_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_CMPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static u64 generic_compat_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) [ C(L1D) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) [ C(L1I) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) [ C(LL) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) [ C(DTLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) [ C(ITLB) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) [ C(BPU) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) [ C(RESULT_ACCESS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) [ C(RESULT_MISS) ] = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) [ C(NODE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) [ C(OP_READ) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [ C(OP_WRITE) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) [ C(OP_PREFETCH) ] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) [ C(RESULT_ACCESS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) [ C(RESULT_MISS) ] = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #undef C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct power_pmu generic_compat_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .name = "GENERIC_COMPAT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .n_counter = MAX_PMU_COUNTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .add_fields = ISA207_ADD_FIELDS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .test_adder = ISA207_TEST_ADDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .compute_mmcr = isa207_compute_mmcr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .get_constraint = isa207_get_constraint,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .disable_pmc = isa207_disable_pmc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .flags = PPMU_HAS_SIER | PPMU_ARCH_207S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .n_generic = ARRAY_SIZE(compat_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .generic_events = compat_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .cache_events = &generic_compat_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .attr_groups = generic_compat_pmu_attr_groups,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int init_generic_compat_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rc = register_power_pmu(&generic_compat_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Tell userspace that EBB is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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