^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for e6500 family processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Priyanka Jain, Priyanka.Jain@freescale.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on e500-pmu.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Map of generic hardware event types to hardware events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Zero if unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) static int e6500_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) [PERF_COUNT_HW_CPU_CYCLES] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) [PERF_COUNT_HW_INSTRUCTIONS] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [PERF_COUNT_HW_CACHE_MISSES] = 221,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) [PERF_COUNT_HW_BRANCH_MISSES] = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static int e6500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [C(L1D)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [C(OP_READ)] = { 27, 222 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [C(OP_WRITE)] = { 28, 223 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [C(OP_PREFETCH)] = { 29, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [C(L1I)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [C(OP_READ)] = { 2, 254 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [C(OP_PREFETCH)] = { 37, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * Assuming LL means L2, it's not a good match for this model.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * It does not have separate read/write events (but it does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * separate instruction/data events).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) [C(LL)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [C(OP_READ)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [C(OP_WRITE)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [C(OP_PREFETCH)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * There are data/instruction MMU misses, but that's a miss on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * the chip's internal level-one TLB which is probably not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * what the user wants. Instead, unified level-two TLB misses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * are reported here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) [C(DTLB)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [C(OP_READ)] = { 26, 66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [C(BPU)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [C(OP_READ)] = { 12, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [C(NODE)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [C(OP_READ)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int num_events = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Upper half of event id is PMLCb, for threshold events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static u64 e6500_xlate_event(u64 event_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 event_low = (u32)event_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (event_low >= num_events ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) (event_id & (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) return FSL_EMB_EVENT_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static struct fsl_emb_pmu e6500_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .name = "e6500 family",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .n_counter = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .n_restricted = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .xlate_event = e6500_xlate_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .n_generic = ARRAY_SIZE(e6500_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .generic_events = e6500_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .cache_events = &e6500_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static int init_e6500_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!cur_cpu_spec->oprofile_cpu_type ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e6500"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return register_fsl_emb_pmu(&e6500_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) early_initcall(init_e6500_pmu);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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