^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance counter support for e500 family processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2010 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Map of generic hardware event types to hardware events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Zero if unsupported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int e500_generic_events[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) [PERF_COUNT_HW_CPU_CYCLES] = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [PERF_COUNT_HW_INSTRUCTIONS] = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) [PERF_COUNT_HW_CACHE_MISSES] = 41, /* Data L1 cache reloads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) [PERF_COUNT_HW_BRANCH_MISSES] = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = 18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = 19,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Table of generalized cache-related events.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * 0 means not supported, -1 means nonsensical, other values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * are event codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int e500_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * D-cache misses are not split into read/write/prefetch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * use raw event 41.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [C(L1D)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) [C(OP_READ)] = { 27, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) [C(OP_WRITE)] = { 28, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) [C(OP_PREFETCH)] = { 29, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) [C(L1I)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) [C(OP_READ)] = { 2, 60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) [C(OP_PREFETCH)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Assuming LL means L2, it's not a good match for this model.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * It allocates only on L1 castout or explicit prefetch, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * does not have separate read/write events (but it does have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * separate instruction/data events).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) [C(LL)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) [C(OP_READ)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) [C(OP_WRITE)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) [C(OP_PREFETCH)] = { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * There are data/instruction MMU misses, but that's a miss on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * the chip's internal level-one TLB which is probably not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * what the user wants. Instead, unified level-two TLB misses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * are reported here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) [C(DTLB)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) [C(OP_READ)] = { 26, 66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) [C(BPU)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) [C(OP_READ)] = { 12, 15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) [C(NODE)] = { /* RESULT_ACCESS RESULT_MISS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) [C(OP_READ)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) [C(OP_WRITE)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) [C(OP_PREFETCH)] = { -1, -1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int num_events = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Upper half of event id is PMLCb, for threshold events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static u64 e500_xlate_event(u64 event_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 event_low = (u32)event_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u64 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (event_low >= num_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ret = FSL_EMB_EVENT_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (event_low >= 76 && event_low <= 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ret |= FSL_EMB_EVENT_RESTRICTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ret |= event_id &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) } else if (event_id &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) (FSL_EMB_EVENT_THRESHMUL | FSL_EMB_EVENT_THRESH)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Threshold requested on non-threshold event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static struct fsl_emb_pmu e500_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "e500 family",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .n_counter = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .n_restricted = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .xlate_event = e500_xlate_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .n_generic = ARRAY_SIZE(e500_generic_events),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .generic_events = e500_generic_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .cache_events = &e500_cache_events,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int init_e500_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!cur_cpu_spec->oprofile_cpu_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500mc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) num_events = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) else if (strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc/e500"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return register_fsl_emb_pmu(&e500_pmu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) early_initcall(init_e500_pmu);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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