^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Performance event support - PPC 8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2016 Christophe Leroy, CS Systemes d'Information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/perf_event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/hardirq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PERF_8xx_ID_CPU_CYCLES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PERF_8xx_ID_HW_INSTRUCTIONS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PERF_8xx_ID_ITLB_LOAD_MISS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PERF_8xx_ID_DTLB_LOAD_MISS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define C(x) PERF_COUNT_HW_CACHE_##x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ITLB_LOAD_MISS (C(ITLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) extern unsigned long itlb_miss_counter, dtlb_miss_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern atomic_t instruction_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static atomic_t insn_ctr_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static atomic_t itlb_miss_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static atomic_t dtlb_miss_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static s64 get_insn_ctr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) int ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned long counta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) ctr = atomic_read(&instruction_counter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) counta = mfspr(SPRN_COUNTA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } while (ctr != atomic_read(&instruction_counter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return ((s64)ctr << 16) | (counta >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int event_type(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) switch (event->attr.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case PERF_TYPE_HARDWARE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) return PERF_8xx_ID_CPU_CYCLES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return PERF_8xx_ID_HW_INSTRUCTIONS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case PERF_TYPE_HW_CACHE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) if (event->attr.config == ITLB_LOAD_MISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return PERF_8xx_ID_ITLB_LOAD_MISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (event->attr.config == DTLB_LOAD_MISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return PERF_8xx_ID_DTLB_LOAD_MISS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case PERF_TYPE_RAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int mpc8xx_pmu_event_init(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int type = event_type(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int mpc8xx_pmu_add(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int type = event_type(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) s64 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) case PERF_8xx_ID_CPU_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val = get_tb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case PERF_8xx_ID_HW_INSTRUCTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (atomic_inc_return(&insn_ctr_ref) == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) mtspr(SPRN_ICTRL, 0xc0080007);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) val = get_insn_ctr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case PERF_8xx_ID_ITLB_LOAD_MISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (atomic_inc_return(&itlb_miss_ref) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long target = patch_site_addr(&patch__itlbmiss_perf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) patch_branch_site(&patch__itlbmiss_exit_1, target, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = itlb_miss_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) case PERF_8xx_ID_DTLB_LOAD_MISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (atomic_inc_return(&dtlb_miss_ref) == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned long target = patch_site_addr(&patch__dtlbmiss_perf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) patch_branch_site(&patch__dtlbmiss_exit_1, target, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = dtlb_miss_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) local64_set(&event->hw.prev_count, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static void mpc8xx_pmu_read(struct perf_event *event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int type = event_type(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) s64 prev, val = 0, delta = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (type < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) prev = local64_read(&event->hw.prev_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case PERF_8xx_ID_CPU_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) val = get_tb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) delta = 16 * (val - prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case PERF_8xx_ID_HW_INSTRUCTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) val = get_insn_ctr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) delta = prev - val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (delta < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) delta += 0x1000000000000LL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) case PERF_8xx_ID_ITLB_LOAD_MISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) val = itlb_miss_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) delta = (s64)((s32)val - (s32)prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case PERF_8xx_ID_DTLB_LOAD_MISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) val = dtlb_miss_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) delta = (s64)((s32)val - (s32)prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) local64_add(delta, &event->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static void mpc8xx_pmu_del(struct perf_event *event, int flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) mpc8xx_pmu_read(event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* If it was the last user, stop counting to avoid useles overhead */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) switch (event_type(event)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) case PERF_8xx_ID_CPU_CYCLES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) case PERF_8xx_ID_HW_INSTRUCTIONS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (atomic_dec_return(&insn_ctr_ref) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) mtspr(SPRN_ICTRL, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) case PERF_8xx_ID_ITLB_LOAD_MISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (atomic_dec_return(&itlb_miss_ref) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* mfspr r10, SPRN_SPRG_SCRATCH0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) __PPC_SPR(SPRN_SPRG_SCRATCH0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) patch_instruction_site(&patch__itlbmiss_exit_1, insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) case PERF_8xx_ID_DTLB_LOAD_MISS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (atomic_dec_return(&dtlb_miss_ref) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* mfspr r10, SPRN_DAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ppc_inst insn = ppc_inst(PPC_INST_MFSPR | __PPC_RS(R10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) __PPC_SPR(SPRN_DAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) patch_instruction_site(&patch__dtlbmiss_exit_1, insn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct pmu mpc8xx_pmu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .event_init = mpc8xx_pmu_event_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .add = mpc8xx_pmu_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .del = mpc8xx_pmu_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .read = mpc8xx_pmu_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .capabilities = PERF_PMU_CAP_NO_INTERRUPT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) PERF_PMU_CAP_NO_NMI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int init_mpc8xx_pmu(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mtspr(SPRN_ICTRL, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) mtspr(SPRN_CMPA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mtspr(SPRN_COUNTA, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return perf_pmu_register(&mpc8xx_pmu, "cpu", PERF_TYPE_RAW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) early_initcall(init_mpc8xx_pmu);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags