^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bpf_jit32.h: BPF JIT compiler for PPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Split from bpf_jit.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _BPF_JIT32_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _BPF_JIT32_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asm-compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "bpf_jit.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BPF_PPC_STACK_R3_OFF 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BPF_PPC_STACK_LOCALS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BPF_PPC_STACK_BASIC (48+64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BPF_PPC_STACK_SAVE (18*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) BPF_PPC_STACK_SAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BPF_PPC_SLOWPATH_FRAME (48+64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BPF_PPC_STACK_R3_OFF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BPF_PPC_STACK_LOCALS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BPF_PPC_STACK_BASIC (24+32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BPF_PPC_STACK_SAVE (18*4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BPF_PPC_STACKFRAME (BPF_PPC_STACK_BASIC+BPF_PPC_STACK_LOCALS+ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) BPF_PPC_STACK_SAVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BPF_PPC_SLOWPATH_FRAME (24+32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_SZ (BITS_PER_LONG/8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * Generated code register usage:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * As normal PPC C ABI (e.g. r1=sp, r2=TOC), with:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * skb r3 (Entry parameter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * A register r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * X register r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * addr param r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * r7-r10 scratch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * skb->data r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * skb headlen r15 (skb->len - skb->data_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * m[0] r16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * m[...] ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * m[15] r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define r_skb 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define r_ret 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define r_A 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define r_X 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define r_addr 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define r_scratch1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define r_scratch2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define r_D 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define r_HL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define r_M 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * Assembly helpers from arch/powerpc/net/bpf_jit.S:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DECLARE_LOAD_FUNC(func) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) extern u8 func[], func##_negative_offset[], func##_positive_offset[]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) DECLARE_LOAD_FUNC(sk_load_word);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) DECLARE_LOAD_FUNC(sk_load_half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DECLARE_LOAD_FUNC(sk_load_byte);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DECLARE_LOAD_FUNC(sk_load_byte_msh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PPC_LBZ_OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_RAW_LBZ(r, base, i)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) else { EMIT(PPC_RAW_ADDIS(r, base, IMM_HA(i))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) EMIT(PPC_RAW_LBZ(r, r, IMM_L(i))); } } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PPC_LD_OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_RAW_LD(r, base, i)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) else { EMIT(PPC_RAW_ADDIS(r, base, IMM_HA(i))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) EMIT(PPC_RAW_LD(r, r, IMM_L(i))); } } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PPC_LWZ_OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_RAW_LWZ(r, base, i)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) else { EMIT(PPC_RAW_ADDIS(r, base, IMM_HA(i))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) EMIT(PPC_RAW_LWZ(r, r, IMM_L(i))); } } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PPC_LHZ_OFFS(r, base, i) do { if ((i) < 32768) EMIT(PPC_RAW_LHZ(r, base, i)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) else { EMIT(PPC_RAW_ADDIS(r, base, IMM_HA(i))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) EMIT(PPC_RAW_LHZ(r, r, IMM_L(i))); } } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PPC_LL_OFFS(r, base, i) do { PPC_LD_OFFS(r, base, i); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define PPC_LL_OFFS(r, base, i) do { PPC_LWZ_OFFS(r, base, i); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define PPC_BPF_LOAD_CPU(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) do { BUILD_BUG_ON(sizeof_field(struct paca_struct, paca_index) != 2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PPC_LHZ_OFFS(r, 13, offsetof(struct paca_struct, paca_index)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define PPC_BPF_LOAD_CPU(r) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) do { BUILD_BUG_ON(sizeof_field(struct task_struct, cpu) != 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PPC_LHZ_OFFS(r, 2, offsetof(struct task_struct, cpu)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PPC_BPF_LOAD_CPU(r) do { EMIT(PPC_RAW_LI(r, 0)); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PPC_LHBRX_OFFS(r, base, i) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) do { PPC_LI32(r, i); EMIT(PPC_RAW_LHBRX(r, r, base)); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #ifdef __LITTLE_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PPC_NTOHS_OFFS(r, base, i) PPC_LHBRX_OFFS(r, base, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PPC_NTOHS_OFFS(r, base, i) PPC_LHZ_OFFS(r, base, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PPC_BPF_LL(r, base, i) do { EMIT(PPC_RAW_LWZ(r, base, i)); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PPC_BPF_STL(r, base, i) do { EMIT(PPC_RAW_STW(r, base, i)); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PPC_BPF_STLU(r, base, i) do { EMIT(PPC_RAW_STWU(r, base, i)); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SEEN_DATAREF 0x10000 /* might call external helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SEEN_XREG 0x20000 /* X reg is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SEEN_MEM 0x40000 /* SEEN_MEM+(1<<n) = use mem[n] for temporary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SEEN_MEM_MSK 0x0ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct codegen_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int seen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int pc_ret0; /* bpf index of first RET #0 instruction (if any) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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