^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * bpf_jit.h: BPF JIT compiler for PPC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Matt Evans <matt@ozlabs.org>, IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * 2016 Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _BPF_JIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _BPF_JIT_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef __ASSEMBLY__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/ppc-opcode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifdef PPC64_ELF_ABI_v1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define FUNCTION_DESCR_SIZE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define FUNCTION_DESCR_SIZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PLANT_INSTR(d, idx, instr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) do { if (d) { (d)[idx] = instr; } idx++; } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EMIT(instr) PLANT_INSTR(image, ctx->idx, instr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Long jump; (unconditional 'branch') */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PPC_JMP(dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) long offset = (long)(dest) - (ctx->idx * 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if (!is_offset_in_branch_range(offset)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) pr_err_ratelimited("Branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) return -ERANGE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) EMIT(PPC_INST_BRANCH | (offset & 0x03fffffc)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* "cond" here covers BO:BI fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PPC_BCC_SHORT(cond, dest) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) long offset = (long)(dest) - (ctx->idx * 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) if (!is_offset_in_cond_branch_range(offset)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) pr_err_ratelimited("Conditional branch offset 0x%lx (@%u) out of range\n", offset, ctx->idx); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) return -ERANGE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) EMIT(PPC_INST_BRANCH_COND | (((cond) & 0x3ff) << 16) | (offset & 0xfffc)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Sign-extended 32-bit immediate load */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PPC_LI32(d, i) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) if ((int)(uintptr_t)(i) >= -32768 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (int)(uintptr_t)(i) < 32768) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) EMIT(PPC_RAW_LI(d, i)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) EMIT(PPC_RAW_LIS(d, IMM_H(i))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (IMM_L(i)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) EMIT(PPC_RAW_ORI(d, d, IMM_L(i))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PPC_LI64(d, i) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) if ((long)(i) >= -2147483648 && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) (long)(i) < 2147483648) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PPC_LI32(d, i); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) if (!((uintptr_t)(i) & 0xffff800000000000ULL)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) EMIT(PPC_RAW_LI(d, ((uintptr_t)(i) >> 32) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 0xffff)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) EMIT(PPC_RAW_LIS(d, ((uintptr_t)(i) >> 48))); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) if ((uintptr_t)(i) & 0x0000ffff00000000ULL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) EMIT(PPC_RAW_ORI(d, d, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) ((uintptr_t)(i) >> 32) & 0xffff)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) EMIT(PPC_RAW_SLDI(d, d, 32)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if ((uintptr_t)(i) & 0x00000000ffff0000ULL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) EMIT(PPC_RAW_ORIS(d, d, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) ((uintptr_t)(i) >> 16) & 0xffff)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if ((uintptr_t)(i) & 0x000000000000ffffULL) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) EMIT(PPC_RAW_ORI(d, d, (uintptr_t)(i) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 0xffff)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) } } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PPC_FUNC_ADDR(d,i) do { PPC_LI64(d, i); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PPC_FUNC_ADDR(d,i) do { PPC_LI32(d, i); } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * The fly in the ointment of code size changing from pass to pass is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * avoided by padding the short branch case with a NOP. If code size differs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * with different branch reaches we will have the issue of code moving from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * one pass to the next and will need a few passes to converge on a stable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PPC_BCC(cond, dest) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (is_offset_in_cond_branch_range((long)(dest) - (ctx->idx * 4))) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PPC_BCC_SHORT(cond, dest); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) EMIT(PPC_RAW_NOP()); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) } else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Flip the 'T or F' bit to invert comparison */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) PPC_BCC_SHORT(cond ^ COND_CMP_TRUE, (ctx->idx+2)*4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) PPC_JMP(dest); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } } while(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* To create a branch condition, select a bit of cr0... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CR0_LT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CR0_GT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CR0_EQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* ...and modify BO[3] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define COND_CMP_TRUE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define COND_CMP_FALSE 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Together, they make all required comparisons: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define COND_GT (CR0_GT | COND_CMP_TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define COND_GE (CR0_LT | COND_CMP_FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define COND_EQ (CR0_EQ | COND_CMP_TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define COND_NE (CR0_EQ | COND_CMP_FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define COND_LT (CR0_LT | COND_CMP_TRUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define COND_LE (CR0_GT | COND_CMP_FALSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif