Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file contains the routines for initializing the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * on the 8xx series of chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  -- christophe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *  Derived from arch/powerpc/mm/40x_mmu.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/hugetlb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/fixmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/inst.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <mm/mmu_decl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define IMMR_SIZE (FIX_IMMR_SIZE << PAGE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) extern int __map_without_ltlbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) static unsigned long block_mapped_ram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * Return PA for this VA if it is in an area mapped with LTLBs or fixmap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * Otherwise, returns 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) phys_addr_t v_block_mapped(unsigned long va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned long p = PHYS_IMMR_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	if (va >= VIRT_IMMR_BASE && va < VIRT_IMMR_BASE + IMMR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 		return p + va - VIRT_IMMR_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	if (__map_without_ltlbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	if (va >= PAGE_OFFSET && va < PAGE_OFFSET + block_mapped_ram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 		return __pa(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43)  * Return VA for a given PA mapped with LTLBs or fixmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44)  * Return 0 if not mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) unsigned long p_block_mapped(phys_addr_t pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned long p = PHYS_IMMR_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	if (pa >= p && pa < p + IMMR_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		return VIRT_IMMR_BASE + pa - p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	if (__map_without_ltlbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	if (pa < block_mapped_ram)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		return (unsigned long)__va(pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) static pte_t __init *early_hugepd_alloc_kernel(hugepd_t *pmdp, unsigned long va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	if (hpd_val(*pmdp) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		pte_t *ptep = memblock_alloc(sizeof(pte_basic_t), SZ_4K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		if (!ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		hugepd_populate_kernel((hugepd_t *)pmdp, ptep, PAGE_SHIFT_8M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		hugepd_populate_kernel((hugepd_t *)pmdp + 1, ptep, PAGE_SHIFT_8M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	return hugepte_offset(*(hugepd_t *)pmdp, va, PGDIR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int __ref __early_map_kernel_hugepage(unsigned long va, phys_addr_t pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 					     pgprot_t prot, int psize, bool new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	pmd_t *pmdp = pmd_off_k(va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	pte_t *ptep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (WARN_ON(psize != MMU_PAGE_512K && psize != MMU_PAGE_8M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		if (WARN_ON(slab_is_available()))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		if (psize == MMU_PAGE_512K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			ptep = early_pte_alloc_kernel(pmdp, va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			ptep = early_hugepd_alloc_kernel((hugepd_t *)pmdp, va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		if (psize == MMU_PAGE_512K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			ptep = pte_offset_kernel(pmdp, va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			ptep = hugepte_offset(*(hugepd_t *)pmdp, va, PGDIR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (WARN_ON(!ptep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	/* The PTE should never be already present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (new && WARN_ON(pte_present(*ptep) && pgprot_val(prot)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	set_huge_pte_at(&init_mm, va, ptep, pte_mkhuge(pfn_pte(pa >> PAGE_SHIFT, prot)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * MMU_init_hw does the chip-specific initialization of the MMU hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __init MMU_init_hw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static bool immr_is_mapped __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __init mmu_mapin_immr(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (immr_is_mapped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	immr_is_mapped = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	__early_map_kernel_hugepage(VIRT_IMMR_BASE, PHYS_IMMR_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				    PAGE_KERNEL_NCG, MMU_PAGE_512K, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static void mmu_mapin_ram_chunk(unsigned long offset, unsigned long top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 				pgprot_t prot, bool new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	unsigned long v = PAGE_OFFSET + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	unsigned long p = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	WARN_ON(!IS_ALIGNED(offset, SZ_512K) || !IS_ALIGNED(top, SZ_512K));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	for (; p < ALIGN(p, SZ_8M) && p < top; p += SZ_512K, v += SZ_512K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		__early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	for (; p < ALIGN_DOWN(top, SZ_8M) && p < top; p += SZ_8M, v += SZ_8M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		__early_map_kernel_hugepage(v, p, prot, MMU_PAGE_8M, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	for (; p < ALIGN_DOWN(top, SZ_512K) && p < top; p += SZ_512K, v += SZ_512K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		__early_map_kernel_hugepage(v, p, prot, MMU_PAGE_512K, new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	if (!new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		flush_tlb_kernel_range(PAGE_OFFSET + v, PAGE_OFFSET + top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	unsigned long sinittext = __pa(_sinittext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	bool strict_boundary = strict_kernel_rwx_enabled() || debug_pagealloc_enabled();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	unsigned long boundary = strict_boundary ? sinittext : etext8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	WARN_ON(top < einittext8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	mmu_mapin_immr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	if (__map_without_ltlbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	mmu_mapin_ram_chunk(0, boundary, PAGE_KERNEL_TEXT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (debug_pagealloc_enabled()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		top = boundary;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL_TEXT, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		mmu_mapin_ram_chunk(einittext8, top, PAGE_KERNEL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (top > SZ_32M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		memblock_set_current_limit(top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	block_mapped_ram = top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void mmu_mark_initmem_nx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	unsigned long etext8 = ALIGN(__pa(_etext), SZ_8M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	unsigned long sinittext = __pa(_sinittext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	unsigned long boundary = strict_kernel_rwx_enabled() ? sinittext : etext8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	unsigned long einittext8 = ALIGN(__pa(_einittext), SZ_8M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mmu_mapin_ram_chunk(0, boundary, PAGE_KERNEL_TEXT, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	mmu_mapin_ram_chunk(boundary, einittext8, PAGE_KERNEL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if (IS_ENABLED(CONFIG_PIN_TLB_TEXT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		mmu_pin_tlb(block_mapped_ram, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #ifdef CONFIG_STRICT_KERNEL_RWX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void mmu_mark_rodata_ro(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	unsigned long sinittext = __pa(_sinittext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	mmu_mapin_ram_chunk(0, sinittext, PAGE_KERNEL_ROX, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (IS_ENABLED(CONFIG_PIN_TLB_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		mmu_pin_tlb(block_mapped_ram, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void __init setup_initial_memory_limit(phys_addr_t first_memblock_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 				       phys_addr_t first_memblock_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	/* We don't currently support the first MEMBLOCK not mapping 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	 * physical on those processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	BUG_ON(first_memblock_base != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	/* 8xx can only access 32MB at the moment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_32M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * Set up to use a given MMU context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * id is context number, pgd is PGD pointer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  * We place the physical address of the new task page directory loaded
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)  * into the MMU base register, and set the ASID compare register with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)  * the new "context."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) void set_context(unsigned long id, pgd_t *pgd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	s16 offset = (s16)(__pa(swapper_pg_dir));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	/* Context switch the PTE pointer for the Abatron BDI2000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	 * The PGDIR is passed as second argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (IS_ENABLED(CONFIG_BDI_SWITCH))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		abatron_pteptrs[1] = pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	/* Register M_TWB will contain base address of level 1 table minus the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	 * lower part of the kernel PGDIR base address, so that all accesses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	 * level 1 table are done relative to lower part of kernel PGDIR base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	 * address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mtspr(SPRN_M_TWB, __pa(pgd) - offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	/* Update context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mtspr(SPRN_M_CASID, id - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	/* sync */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_PPC_KUEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void __init setup_kuep(bool disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	pr_info("Activating Kernel Userspace Execution Prevention\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	mtspr(SPRN_MI_AP, MI_APG_KUEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #ifdef CONFIG_PPC_KUAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) void __init setup_kuap(bool disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	pr_info("Activating Kernel Userspace Access Protection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	if (disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		pr_warn("KUAP cannot be disabled yet on 8xx when compiled in\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	mtspr(SPRN_MD_AP, MD_APG_KUAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #endif