^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Modifications by Matt Porter (mporter@mvista.com) to support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PPC44x Book E processors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file contains the routines for initializing the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * on the 4xx series of chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * -- paulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Derived from arch/ppc/mm/init.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * and Cort Dougan (PReP) (cort@cs.nmt.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1996 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Derived from "arch/i386/mm/init.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mm/mmu_decl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Used by the 44x TLB replacement exception handler.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * Just needed it declared someplace.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int tlb_44x_index; /* = 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int tlb_44x_hwater = PPC44x_TLB_SIZE - 1 - PPC44x_EARLY_TLBS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) int icache_44x_need_flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long tlb_47x_boltmap[1024/8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) static void ppc44x_update_tlb_hwater(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* The TLB miss handlers hard codes the watermark in a cmpli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * instruction to improve performances rather than loading it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * from the global variable. Thus, we patch the instructions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * in the 2 TLB miss handlers when updating the value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) modify_instruction_site(&patch__tlb_44x_hwater_D, 0xffff, tlb_44x_hwater);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) modify_instruction_site(&patch__tlb_44x_hwater_I, 0xffff, tlb_44x_hwater);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 44x type MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static void __init ppc44x_pin_tlb(unsigned int virt, unsigned int phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned int entry = tlb_44x_hwater--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) ppc44x_update_tlb_hwater();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) mtspr(SPRN_MMUCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "tlbwe %2,%3,%4\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "tlbwe %1,%3,%5\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "tlbwe %0,%3,%6\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) : "r" (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "r" (phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "r" (virt | PPC44x_TLB_VALID | PPC44x_TLB_256M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "r" (entry),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "i" (PPC44x_TLB_PAGEID),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "i" (PPC44x_TLB_XLAT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "i" (PPC44x_TLB_ATTRIB));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static int __init ppc47x_find_free_bolted(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int mmube0 = mfspr(SPRN_MMUBE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) unsigned int mmube1 = mfspr(SPRN_MMUBE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!(mmube0 & MMUBE0_VBE0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!(mmube0 & MMUBE0_VBE1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (!(mmube0 & MMUBE0_VBE2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!(mmube1 & MMUBE1_VBE3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!(mmube1 & MMUBE1_VBE4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!(mmube1 & MMUBE1_VBE5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static void __init ppc47x_update_boltmap(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int mmube0 = mfspr(SPRN_MMUBE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int mmube1 = mfspr(SPRN_MMUBE1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (mmube0 & MMUBE0_VBE0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) __set_bit((mmube0 >> MMUBE0_IBE0_SHIFT) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tlb_47x_boltmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (mmube0 & MMUBE0_VBE1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) __set_bit((mmube0 >> MMUBE0_IBE1_SHIFT) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) tlb_47x_boltmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (mmube0 & MMUBE0_VBE2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) __set_bit((mmube0 >> MMUBE0_IBE2_SHIFT) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) tlb_47x_boltmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (mmube1 & MMUBE1_VBE3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) __set_bit((mmube1 >> MMUBE1_IBE3_SHIFT) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tlb_47x_boltmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (mmube1 & MMUBE1_VBE4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) __set_bit((mmube1 >> MMUBE1_IBE4_SHIFT) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tlb_47x_boltmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (mmube1 & MMUBE1_VBE5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) __set_bit((mmube1 >> MMUBE1_IBE5_SHIFT) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) tlb_47x_boltmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * "Pins" a 256MB TLB entry in AS0 for kernel lowmem for 47x type MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void ppc47x_pin_tlb(unsigned int virt, unsigned int phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int rA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int bolted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Base rA is HW way select, way 0, bolted bit set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) rA = 0x88000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Look for a bolted entry slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) bolted = ppc47x_find_free_bolted();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) BUG_ON(bolted < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Insert bolted slot number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rA |= bolted << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) pr_debug("256M TLB entry for 0x%08x->0x%08x in bolt slot %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) virt, phys, bolted);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) mtspr(SPRN_MMUCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) __asm__ __volatile__(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "tlbwe %2,%3,0\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "tlbwe %1,%3,1\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "tlbwe %0,%3,2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) : "r" (PPC47x_TLB2_SW | PPC47x_TLB2_SR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) PPC47x_TLB2_SX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) | PPC47x_TLB2_M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) "r" (phys),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "r" (virt | PPC47x_TLB0_VALID | PPC47x_TLB0_256M),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "r" (rA));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __init MMU_init_hw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* This is not useful on 47x but won't hurt either */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ppc44x_update_tlb_hwater();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) flush_instruction_cache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Pin in enough TLBs to cover any lowmem not covered by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * initial 256M mapping established in head_44x.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) addr += PPC_PIN_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (mmu_has_feature(MMU_FTR_TYPE_47x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (mmu_has_feature(MMU_FTR_TYPE_47x)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ppc47x_update_boltmap();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) printk(KERN_DEBUG "bolted entries: ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) for (i = 0; i < 255; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (test_bit(i, tlb_47x_boltmap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) printk("%d ", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif /* DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return total_lowmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void setup_initial_memory_limit(phys_addr_t first_memblock_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) phys_addr_t first_memblock_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u64 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #ifndef CONFIG_NONSTATIC_KERNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* We don't currently support the first MEMBLOCK not mapping 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * physical on those processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) BUG_ON(first_memblock_base != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 44x has a 256M TLB entry pinned at boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) size = (min_t(u64, first_memblock_size, PPC_PIN_SIZE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) memblock_set_current_limit(first_memblock_base + size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #ifdef CONFIG_SMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) void __init mmu_init_secondary(int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned long addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) unsigned long memstart = memstart_addr & ~(PPC_PIN_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Pin in enough TLBs to cover any lowmem not covered by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * initial 256M mapping established in head_44x.S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * WARNING: This is called with only the first 256M of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * linear mapping in the TLB and we can't take faults yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * so beware of what this code uses. It runs off a temporary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * stack. current (r2) isn't initialized, smp_processor_id()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * will not work, current thread info isn't accessible, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (addr = memstart + PPC_PIN_SIZE; addr < lowmem_end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) addr += PPC_PIN_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (mmu_has_feature(MMU_FTR_TYPE_47x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ppc47x_pin_tlb(addr + PAGE_OFFSET, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ppc44x_pin_tlb(addr + PAGE_OFFSET, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #endif /* CONFIG_SMP */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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