^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file contains the routines for initializing the MMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * on the 4xx series of chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * -- paulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from arch/ppc/mm/init.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * and Cort Dougan (PReP) (cort@cs.nmt.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 1996 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Derived from "arch/i386/mm/init.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/signal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/mman.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/swap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/vmalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <asm/bootx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <asm/setup.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <mm/mmu_decl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) extern int __map_without_ltlbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * MMU_init_hw does the chip-specific initialization of the MMU hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) void __init MMU_init_hw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * The Zone Protection Register (ZPR) defines how protection will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * be applied to every page which is a member of a given zone. At
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * present, we utilize only two of the 4xx's zones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * The zone index bits (of ZSEL) in the PTE are used for software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * indicators, except the LSB. For user access, zone 1 is used,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * for kernel access, zone 0 is used. We set all but zone 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * to zero, allowing only kernel access as indicated in the PTE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * For zone 1, we set a 01 binary (a value of 10 will not work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * to allow user access as indicated in the PTE. This also allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * kernel access as indicated in the PTE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mtspr(SPRN_ZPR, 0x10000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) flush_instruction_cache();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Set up the real-mode cache parameters for the exception vector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * handlers (which are run in real-mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * Cache instruction and data space where the exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * vectors and the kernel live in real-mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mtspr(SPRN_DCCR, 0xFFFF0000); /* 2GByte of data space at 0x0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mtspr(SPRN_ICCR, 0xFFFF0000); /* 2GByte of instr. space at 0x0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LARGE_PAGE_SIZE_16M (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LARGE_PAGE_SIZE_4M (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long v, s, mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) phys_addr_t p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) v = KERNELBASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) p = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) s = total_lowmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (__map_without_ltlbs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) while (s >= LARGE_PAGE_SIZE_16M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pmd_t *pmdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned long val = p | _PMD_SIZE_16M | _PAGE_EXEC | _PAGE_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) pmdp = pmd_off_k(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) *pmdp++ = __pmd(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) *pmdp++ = __pmd(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) *pmdp++ = __pmd(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) *pmdp++ = __pmd(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) v += LARGE_PAGE_SIZE_16M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) p += LARGE_PAGE_SIZE_16M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) s -= LARGE_PAGE_SIZE_16M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) while (s >= LARGE_PAGE_SIZE_4M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) pmd_t *pmdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long val = p | _PMD_SIZE_4M | _PAGE_EXEC | _PAGE_RW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) pmdp = pmd_off_k(v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) *pmdp = __pmd(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) v += LARGE_PAGE_SIZE_4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) p += LARGE_PAGE_SIZE_4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) s -= LARGE_PAGE_SIZE_4M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) mapped = total_lowmem - s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* If the size of RAM is not an exact power of two, we may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * have covered RAM in its entirety with 16 and 4 MiB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * pages. Consequently, restrict the top end of RAM currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * allocable so that calls to the MEMBLOCK to allocate PTEs for "tail"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * coverage with normal-sized pages (or other reasons) do not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * attempt to allocate outside the allowed range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) memblock_set_current_limit(mapped);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return mapped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void setup_initial_memory_limit(phys_addr_t first_memblock_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) phys_addr_t first_memblock_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* We don't currently support the first MEMBLOCK not mapping 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * physical on those processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) BUG_ON(first_memblock_base != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* 40x can only access 16MB at the moment (see head_40x.S) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) memblock_set_current_limit(min_t(u64, first_memblock_size, 0x00800000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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