Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Declarations of procedures and variables shared between files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * in arch/ppc/mm/.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Derived from arch/ppc/mm/init.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *    Copyright (C) 1996 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *  Derived from "arch/i386/mm/init.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #ifdef CONFIG_PPC_MMU_NOHASH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <asm/trace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * On 40x and 8xx, we directly inline tlbia and tlbivax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #if defined(CONFIG_40x) || defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static inline void _tlbil_all(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	asm volatile ("sync; tlbia; isync" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	trace_tlbia(MMU_NO_CONTEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) static inline void _tlbil_pid(unsigned int pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	asm volatile ("sync; tlbia; isync" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	trace_tlbia(pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define _tlbil_pid_noind(pid)	_tlbil_pid(pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #else /* CONFIG_40x || CONFIG_PPC_8xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) extern void _tlbil_all(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) extern void _tlbil_pid(unsigned int pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #ifdef CONFIG_PPC_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) extern void _tlbil_pid_noind(unsigned int pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define _tlbil_pid_noind(pid)	_tlbil_pid(pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #endif /* !(CONFIG_40x || CONFIG_PPC_8xx) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49)  * On 8xx, we directly inline tlbie, on others, it's extern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static inline void _tlbil_va(unsigned long address, unsigned int pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 			     unsigned int tsize, unsigned int ind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	asm volatile ("tlbie %0; sync" : : "r" (address) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	trace_tlbie(0, 0, address, pid, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #elif defined(CONFIG_PPC_BOOK3E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) extern void _tlbil_va(unsigned long address, unsigned int pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		      unsigned int tsize, unsigned int ind);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) extern void __tlbil_va(unsigned long address, unsigned int pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static inline void _tlbil_va(unsigned long address, unsigned int pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 			     unsigned int tsize, unsigned int ind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__tlbil_va(address, pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #endif /* CONFIG_PPC_8xx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #if defined(CONFIG_PPC_BOOK3E) || defined(CONFIG_PPC_47x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) extern void _tlbivax_bcast(unsigned long address, unsigned int pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 			   unsigned int tsize, unsigned int ind);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static inline void _tlbivax_bcast(unsigned long address, unsigned int pid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 				   unsigned int tsize, unsigned int ind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static inline void print_system_hash_info(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #else /* CONFIG_PPC_MMU_NOHASH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) extern void _tlbie(unsigned long address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) extern void _tlbia(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) void print_system_hash_info(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #endif /* CONFIG_PPC_MMU_NOHASH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) void hash_preload(struct mm_struct *mm, unsigned long ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) extern void mapin_ram(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) extern void setbat(int index, unsigned long virt, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		   unsigned int size, pgprot_t prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) extern int __map_without_bats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) extern unsigned int rtas_data, rtas_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct hash_pte;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) extern struct hash_pte *Hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) extern u8 early_hash[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #endif /* CONFIG_PPC32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) extern unsigned long __max_low_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) extern phys_addr_t __initial_memory_limit_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) extern phys_addr_t total_memory;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) extern phys_addr_t total_lowmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) extern phys_addr_t memstart_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) extern phys_addr_t lowmem_end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef CONFIG_WII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) extern unsigned long wii_hole_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) extern unsigned long wii_hole_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) extern unsigned long wii_mmu_mapin_mem2(unsigned long top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) extern void wii_memory_fixups(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* ...and now those things that may be slightly different between processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)  * architectures.  -- Dan
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) extern void MMU_init_hw(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void MMU_init_hw_patch(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long mmu_mapin_ram(unsigned long base, unsigned long top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) extern unsigned long map_mem_in_cams(unsigned long ram, int max_cam_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 				     bool dryrun);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) extern unsigned long calc_cam_sz(unsigned long ram, unsigned long virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 				 phys_addr_t phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #ifdef CONFIG_PPC32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) extern void adjust_total_lowmem(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) extern int switch_to_as1(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) extern void restore_to_as0(int esel, int offset, void *dt_ptr, int bootcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) void create_kaslr_tlb_entry(int entry, unsigned long virt, phys_addr_t phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) void reloc_kernel_entry(void *fdt, int addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) extern int is_second_reloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) extern void loadcam_entry(unsigned int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) extern void loadcam_multi(int first_idx, int num, int tmp_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #ifdef CONFIG_RANDOMIZE_BASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) void kaslr_early_init(void *dt_ptr, phys_addr_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) void kaslr_late_init(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static inline void kaslr_early_init(void *dt_ptr, phys_addr_t size) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void kaslr_late_init(void) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct tlbcam {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	u32	MAS0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	u32	MAS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned long	MAS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	u32	MAS3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u32	MAS7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_FSL_BOOKE) || defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 6xx have BATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* FSL_BOOKE have TLBCAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* 8xx have LTLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) phys_addr_t v_block_mapped(unsigned long va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned long p_block_mapped(phys_addr_t pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static inline phys_addr_t v_block_mapped(unsigned long va) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline unsigned long p_block_mapped(phys_addr_t pa) { return 0; }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #if defined(CONFIG_PPC_BOOK3S_32) || defined(CONFIG_PPC_8xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) void mmu_mark_initmem_nx(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) void mmu_mark_rodata_ro(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline void mmu_mark_initmem_nx(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline void mmu_mark_rodata_ro(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef CONFIG_PPC_8xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) void __init mmu_mapin_immr(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #ifdef CONFIG_PPC_DEBUG_WX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) void ptdump_check_wx(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline void ptdump_check_wx(void) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif