^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Common implementation of switch_mm_irqs_off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright IBM Corp. 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/sched/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/pgalloc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #if defined(CONFIG_PPC32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) static inline void switch_mm_pgdir(struct task_struct *tsk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* 32-bit keeps track of the current PGDIR in the thread struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) tsk->thread.pgdir = mm->pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #elif defined(CONFIG_PPC_BOOK3E_64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static inline void switch_mm_pgdir(struct task_struct *tsk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* 64-bit Book3E keeps track of current PGD in the PACA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) get_paca()->pgd = mm->pgd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static inline void switch_mm_pgdir(struct task_struct *tsk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mm_struct *mm) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct task_struct *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) bool new_on_cpu = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Mark this context has been used on the new CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) inc_mm_active_cpus(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * This full barrier orders the store to the cpumask above vs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * a subsequent operation which allows this CPU to begin loading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * translations for next.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * When using the radix MMU that operation is the load of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * MMU context id, which is then moved to SPRN_PID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * For the hash MMU it is either the first load from slb_cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * in switch_slb(), and/or the store of paca->mm_ctx_id in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * copy_mm_to_paca().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * On the other side, the barrier is in mm/tlb-radix.c for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * radix which orders earlier stores to clear the PTEs vs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * the load of mm_cpumask. And pte_xchg which does the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * thing for hash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * This full barrier is needed by membarrier when switching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * between processes after store to rq->curr, before user-space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * memory accesses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) smp_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) new_on_cpu = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Some subarchs need to track the PGD elsewhere */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) switch_mm_pgdir(tsk, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Nothing else to do if we aren't actually switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (prev == next)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * We must stop all altivec streams before changing the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (cpu_has_feature(CPU_FTR_ALTIVEC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) asm volatile ("dssall");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) if (new_on_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) radix_kvm_prefetch_workaround(next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) membarrier_arch_switch_mm(prev, next, tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * The actual HW switching method differs between the various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * sub architectures. Out of line for now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch_mmu_context(prev, next, tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #ifndef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) void arch_exit_mmap(struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) void *frag = pte_frag_get(&mm->context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (frag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) pte_frag_destroy(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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