^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PowerPC64 SLB support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on earlier code written by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2001 Dave Engebretsen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/asm-prototypes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/mmu_context.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/paca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/ppc-opcode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/cacheflush.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/compiler.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/context_tracking.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mm_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <asm/udbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) enum slb_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) LINEAR_INDEX = 0, /* Kernel linear map (0xc000000000000000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) KSTACK_INDEX = 1, /* Kernel stack map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static long slb_allocate_user(struct mm_struct *mm, unsigned long ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define slb_esid_mask(ssize) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) (((ssize) == MMU_SEGSIZE_256M)? ESID_MASK: ESID_MASK_1T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static inline unsigned long mk_esid_data(unsigned long ea, int ssize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum slb_index index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return (ea & slb_esid_mask(ssize)) | SLB_ESID_V | index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static inline unsigned long __mk_vsid_data(unsigned long vsid, int ssize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return (vsid << slb_vsid_shift(ssize)) | flags |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ((unsigned long) ssize << SLB_VSID_SSIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) static inline unsigned long mk_vsid_data(unsigned long ea, int ssize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return __mk_vsid_data(get_kernel_vsid(ea, ssize), ssize, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) bool stress_slb_enabled __initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static int __init parse_stress_slb(char *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) stress_slb_enabled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) early_param("stress_slb", parse_stress_slb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __ro_after_init DEFINE_STATIC_KEY_FALSE(stress_slb_key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static void assert_slb_presence(bool present, unsigned long ea)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #ifdef CONFIG_DEBUG_VM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned long tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) WARN_ON_ONCE(mfmsr() & MSR_EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (!cpu_has_feature(CPU_FTR_ARCH_206))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * slbfee. requires bit 24 (PPC bit 39) be clear in RB. Hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * ignores all other bits from 0-27, so just clear them all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) ea &= ~((1UL << SID_SHIFT) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) asm volatile(__PPC_SLBFEE_DOT(%0, %1) : "=r"(tmp) : "r"(ea) : "cr0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) WARN_ON(present == (tmp == 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) static inline void slb_shadow_update(unsigned long ea, int ssize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) enum slb_index index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct slb_shadow *p = get_slb_shadow();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Clear the ESID first so the entry is not valid while we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * updating it. No write barriers are needed here, provided
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * we only update the current CPU's SLB shadow buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) WRITE_ONCE(p->save_area[index].esid, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) WRITE_ONCE(p->save_area[index].vsid, cpu_to_be64(mk_vsid_data(ea, ssize, flags)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) WRITE_ONCE(p->save_area[index].esid, cpu_to_be64(mk_esid_data(ea, ssize, index)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static inline void slb_shadow_clear(enum slb_index index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) WRITE_ONCE(get_slb_shadow()->save_area[index].esid, cpu_to_be64(index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static inline void create_shadowed_slbe(unsigned long ea, int ssize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned long flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) enum slb_index index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * Updating the shadow buffer before writing the SLB ensures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * we don't get a stale entry here if we get preempted by PHYP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * between these two statements.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) slb_shadow_update(ea, ssize, flags, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) assert_slb_presence(false, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) asm volatile("slbmte %0,%1" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) : "r" (mk_vsid_data(ea, ssize, flags)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) "r" (mk_esid_data(ea, ssize, index))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) : "memory" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * Insert bolted entries into SLB (which may not be empty, so don't clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * slb_cache_ptr).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __slb_restore_bolted_realmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct slb_shadow *p = get_slb_shadow();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) enum slb_index index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* No isync needed because realmode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (index = 0; index < SLB_NUM_BOLTED; index++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) asm volatile("slbmte %0,%1" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) : "r" (be64_to_cpu(p->save_area[index].vsid)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "r" (be64_to_cpu(p->save_area[index].esid)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) assert_slb_presence(true, local_paca->kstack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * Insert the bolted entries into an empty SLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) void slb_restore_bolted_realmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) __slb_restore_bolted_realmode();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) get_paca()->slb_cache_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * This flushes all SLB entries including 0, so it must be realmode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) void slb_flush_all_realmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) asm volatile("slbmte %0,%0; slbia" : : "r" (0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static __always_inline void __slb_flush_and_restore_bolted(bool preserve_kernel_lookaside)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct slb_shadow *p = get_slb_shadow();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned long ksp_esid_data, ksp_vsid_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u32 ih;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * SLBIA IH=1 on ISA v2.05 and newer processors may preserve lookaside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * information created with Class=0 entries, which we use for kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * SLB entries (the SLB entries themselves are still invalidated).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Older processors will ignore this optimisation. Over-invalidation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * is fine because we never rely on lookaside information existing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (preserve_kernel_lookaside)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ih = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ih = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ksp_esid_data = be64_to_cpu(p->save_area[KSTACK_INDEX].esid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ksp_vsid_data = be64_to_cpu(p->save_area[KSTACK_INDEX].vsid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) asm volatile(PPC_SLBIA(%0)" \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) "slbmte %1, %2 \n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) :: "i" (ih),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) "r" (ksp_vsid_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "r" (ksp_esid_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * This flushes non-bolted entries, it can be run in virtual mode. Must
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * be called with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) void slb_flush_and_restore_bolted(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) BUILD_BUG_ON(SLB_NUM_BOLTED != 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) WARN_ON(!irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * We can't take a PMU exception in the following code, so hard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * disable interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) hard_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) isync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) __slb_flush_and_restore_bolted(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) isync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) assert_slb_presence(true, get_paca()->kstack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) get_paca()->slb_cache_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) void slb_save_contents(struct slb_entry *slb_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) unsigned long e, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Save slb_cache_ptr value. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) get_paca()->slb_save_cache_ptr = get_paca()->slb_cache_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (!slb_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 0; i < mmu_slb_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) asm volatile("slbmfee %0,%1" : "=r" (e) : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) asm volatile("slbmfev %0,%1" : "=r" (v) : "r" (i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) slb_ptr->esid = e;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) slb_ptr->vsid = v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) slb_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void slb_dump_contents(struct slb_entry *slb_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int i, n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) unsigned long e, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) unsigned long llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (!slb_ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) pr_err("SLB contents of cpu 0x%x\n", smp_processor_id());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) pr_err("Last SLB entry inserted at slot %d\n", get_paca()->stab_rr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 0; i < mmu_slb_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) e = slb_ptr->esid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) v = slb_ptr->vsid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) slb_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if (!e && !v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) pr_err("%02d %016lx %016lx\n", i, e, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (!(e & SLB_ESID_V)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) pr_err("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) llp = v & SLB_VSID_LLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (v & SLB_VSID_B_1T) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) pr_err(" 1T ESID=%9lx VSID=%13lx LLP:%3lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) GET_ESID_1T(e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (v & ~SLB_VSID_B) >> SLB_VSID_SHIFT_1T, llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pr_err(" 256M ESID=%9lx VSID=%13lx LLP:%3lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) GET_ESID(e),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) (v & ~SLB_VSID_B) >> SLB_VSID_SHIFT, llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) pr_err("----------------------------------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* Dump slb cache entires as well. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) pr_err("SLB cache ptr value = %d\n", get_paca()->slb_save_cache_ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) pr_err("Valid SLB cache entries:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) n = min_t(int, get_paca()->slb_save_cache_ptr, SLB_CACHE_ENTRIES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) pr_err("%02d EA[0-35]=%9x\n", i, get_paca()->slb_cache[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) pr_err("Rest of SLB cache entries:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) for (i = n; i < SLB_CACHE_ENTRIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) pr_err("%02d EA[0-35]=%9x\n", i, get_paca()->slb_cache[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) void slb_vmalloc_update(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * vmalloc is not bolted, so just have to flush non-bolted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) slb_flush_and_restore_bolted();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static bool preload_hit(struct thread_info *ti, unsigned long esid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned char i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (i = 0; i < ti->slb_preload_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned char idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) idx = (ti->slb_preload_tail + i) % SLB_PRELOAD_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (esid == ti->slb_preload_esid[idx])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static bool preload_add(struct thread_info *ti, unsigned long ea)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned char idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned long esid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (mmu_has_feature(MMU_FTR_1T_SEGMENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* EAs are stored >> 28 so 256MB segments don't need clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ea & ESID_MASK_1T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ea &= ESID_MASK_1T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) esid = ea >> SID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (preload_hit(ti, esid))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) idx = (ti->slb_preload_tail + ti->slb_preload_nr) % SLB_PRELOAD_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ti->slb_preload_esid[idx] = esid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (ti->slb_preload_nr == SLB_PRELOAD_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ti->slb_preload_tail = (ti->slb_preload_tail + 1) % SLB_PRELOAD_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ti->slb_preload_nr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void preload_age(struct thread_info *ti)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!ti->slb_preload_nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ti->slb_preload_nr--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) ti->slb_preload_tail = (ti->slb_preload_tail + 1) % SLB_PRELOAD_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) void slb_setup_new_exec(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct thread_info *ti = current_thread_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct mm_struct *mm = current->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) unsigned long exec = 0x10000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) WARN_ON(irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * preload cache can only be used to determine whether a SLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * entry exists if it does not start to overflow.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (ti->slb_preload_nr + 2 > SLB_PRELOAD_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) hard_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * We have no good place to clear the slb preload cache on exec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * flush_thread is about the earliest arch hook but that happens
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * after we switch to the mm and have aleady preloaded the SLBEs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * For the most part that's probably okay to use entries from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * previous exec, they will age out if unused. It may turn out to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) * be an advantage to clear the cache before switching to it,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) * however.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * preload some userspace segments into the SLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Almost all 32 and 64bit PowerPC executables are linked at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * 0x10000000 so it makes sense to preload this segment.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!is_kernel_addr(exec)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (preload_add(ti, exec))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) slb_allocate_user(mm, exec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Libraries and mmaps. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!is_kernel_addr(mm->mmap_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (preload_add(ti, mm->mmap_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) slb_allocate_user(mm, mm->mmap_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* see switch_slb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) asm volatile("isync" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void preload_new_slb_context(unsigned long start, unsigned long sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct thread_info *ti = current_thread_info();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct mm_struct *mm = current->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned long heap = mm->start_brk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) WARN_ON(irqs_disabled());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* see above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ti->slb_preload_nr + 3 > SLB_PRELOAD_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) hard_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* Userspace entry address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!is_kernel_addr(start)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (preload_add(ti, start))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) slb_allocate_user(mm, start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Top of stack, grows down. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!is_kernel_addr(sp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (preload_add(ti, sp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) slb_allocate_user(mm, sp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Bottom of heap, grows up. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (heap && !is_kernel_addr(heap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (preload_add(ti, heap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) slb_allocate_user(mm, heap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* see switch_slb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) asm volatile("isync" : : : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) local_irq_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static void slb_cache_slbie_kernel(unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned long slbie_data = get_paca()->slb_cache[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned long ksp = get_paca()->kstack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) slbie_data <<= SID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) slbie_data |= 0xc000000000000000ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if ((ksp & slb_esid_mask(mmu_kernel_ssize)) == slbie_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) slbie_data |= mmu_kernel_ssize << SLBIE_SSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) asm volatile("slbie %0" : : "r" (slbie_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static void slb_cache_slbie_user(unsigned int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned long slbie_data = get_paca()->slb_cache[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) slbie_data <<= SID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) slbie_data |= user_segment_size(slbie_data) << SLBIE_SSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) slbie_data |= SLBIE_C; /* user slbs have C=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) asm volatile("slbie %0" : : "r" (slbie_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* Flush all user entries from the segment table of the current processor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct thread_info *ti = task_thread_info(tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned char i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * We need interrupts hard-disabled here, not just soft-disabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * so that a PMU interrupt can't occur, which might try to access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * user memory (to get a stack trace) and possible cause an SLB miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * which would update the slb_cache/slb_cache_ptr fields in the PACA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) hard_irq_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) isync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (stress_slb()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) __slb_flush_and_restore_bolted(false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) isync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) get_paca()->slb_cache_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } else if (cpu_has_feature(CPU_FTR_ARCH_300)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) * SLBIA IH=3 invalidates all Class=1 SLBEs and their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * associated lookaside structures, which matches what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * switch_slb wants. So ARCH_300 does not use the slb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) * cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) asm volatile(PPC_SLBIA(3));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) unsigned long offset = get_paca()->slb_cache_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (!mmu_has_feature(MMU_FTR_NO_SLBIE_B) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) offset <= SLB_CACHE_ENTRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Could assert_slb_presence(true) here, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * hypervisor or machine check could have come
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * in and removed the entry at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (i = 0; i < offset; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) slb_cache_slbie_user(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Workaround POWER5 < DD2.1 issue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!cpu_has_feature(CPU_FTR_ARCH_207S) && offset == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) slb_cache_slbie_user(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Flush but retain kernel lookaside information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) __slb_flush_and_restore_bolted(true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) isync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) get_paca()->slb_cache_ptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) copy_mm_to_paca(mm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * We gradually age out SLBs after a number of context switches to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * reduce reload overhead of unused entries (like we do with FP/VEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * reload). Each time we wrap 256 switches, take an entry out of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * SLB preload cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) tsk->thread.load_slb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!tsk->thread.load_slb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) unsigned long pc = KSTK_EIP(tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) preload_age(ti);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) preload_add(ti, pc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) for (i = 0; i < ti->slb_preload_nr; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned char idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned long ea;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) idx = (ti->slb_preload_tail + i) % SLB_PRELOAD_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ea = (unsigned long)ti->slb_preload_esid[idx] << SID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) slb_allocate_user(mm, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) * Synchronize slbmte preloads with possible subsequent user memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * address accesses by the kernel (user mode won't happen until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * rfid, which is safe).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) isync();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) void slb_set_size(u16 size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mmu_slb_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) void slb_initialize(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) unsigned long linear_llp, vmalloc_llp, io_llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned long lflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static int slb_encoding_inited;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #ifdef CONFIG_SPARSEMEM_VMEMMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned long vmemmap_llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Prepare our SLB miss handler based on our page size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) linear_llp = mmu_psize_defs[mmu_linear_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) io_llp = mmu_psize_defs[mmu_io_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) vmalloc_llp = mmu_psize_defs[mmu_vmalloc_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) get_paca()->vmalloc_sllp = SLB_VSID_KERNEL | vmalloc_llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #ifdef CONFIG_SPARSEMEM_VMEMMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) vmemmap_llp = mmu_psize_defs[mmu_vmemmap_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!slb_encoding_inited) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) slb_encoding_inited = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pr_devel("SLB: linear LLP = %04lx\n", linear_llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) pr_devel("SLB: io LLP = %04lx\n", io_llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #ifdef CONFIG_SPARSEMEM_VMEMMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pr_devel("SLB: vmemmap LLP = %04lx\n", vmemmap_llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) get_paca()->stab_rr = SLB_NUM_BOLTED - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) get_paca()->slb_kern_bitmap = (1U << SLB_NUM_BOLTED) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) get_paca()->slb_used_bitmap = get_paca()->slb_kern_bitmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) lflags = SLB_VSID_KERNEL | linear_llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* Invalidate the entire SLB (even entry 0) & all the ERATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) asm volatile("isync":::"memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) asm volatile("slbmte %0,%0"::"r" (0) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) asm volatile("isync; slbia; isync":::"memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) create_shadowed_slbe(PAGE_OFFSET, mmu_kernel_ssize, lflags, LINEAR_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * For the boot cpu, we're running on the stack in init_thread_union,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * which is in the first segment of the linear mapping, and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * get_paca()->kstack hasn't been initialized yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) * For secondary cpus, we need to bolt the kernel stack entry now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) slb_shadow_clear(KSTACK_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (raw_smp_processor_id() != boot_cpuid &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) (get_paca()->kstack & slb_esid_mask(mmu_kernel_ssize)) > PAGE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) create_shadowed_slbe(get_paca()->kstack,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mmu_kernel_ssize, lflags, KSTACK_INDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) asm volatile("isync":::"memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static void slb_cache_update(unsigned long esid_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int slb_cache_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (cpu_has_feature(CPU_FTR_ARCH_300))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return; /* ISAv3.0B and later does not use slb_cache */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (stress_slb())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * Now update slb cache entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) slb_cache_index = local_paca->slb_cache_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (slb_cache_index < SLB_CACHE_ENTRIES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) * We have space in slb cache for optimized switch_slb().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * Top 36 bits from esid_data as per ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) local_paca->slb_cache[slb_cache_index++] = esid_data >> SID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) local_paca->slb_cache_ptr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) * Our cache is full and the current cache content strictly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * doesn't indicate the active SLB conents. Bump the ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * so that switch_slb() will ignore the cache.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) local_paca->slb_cache_ptr = SLB_CACHE_ENTRIES + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static enum slb_index alloc_slb_index(bool kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) enum slb_index index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * The allocation bitmaps can become out of synch with the SLB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * when the _switch code does slbie when bolting a new stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * segment and it must not be anywhere else in the SLB. This leaves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * a kernel allocated entry that is unused in the SLB. With very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * large systems or small segment sizes, the bitmaps could slowly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * fill with these entries. They will eventually be cleared out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * by the round robin allocator in that case, so it's probably not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * worth accounting for.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * SLBs beyond 32 entries are allocated with stab_rr only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * POWER7/8/9 have 32 SLB entries, this could be expanded if a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * future CPU has more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (local_paca->slb_used_bitmap != U32_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) index = ffz(local_paca->slb_used_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) local_paca->slb_used_bitmap |= 1U << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) local_paca->slb_kern_bitmap |= 1U << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* round-robin replacement of slb starting at SLB_NUM_BOLTED. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) index = local_paca->stab_rr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (index < (mmu_slb_size - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) index = SLB_NUM_BOLTED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) local_paca->stab_rr = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (index < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) local_paca->slb_kern_bitmap |= 1U << index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) local_paca->slb_kern_bitmap &= ~(1U << index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) BUG_ON(index < SLB_NUM_BOLTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static long slb_insert_entry(unsigned long ea, unsigned long context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned long flags, int ssize, bool kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) unsigned long vsid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned long vsid_data, esid_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) enum slb_index index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) vsid = get_vsid(context, ea, ssize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!vsid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * There must not be a kernel SLB fault in alloc_slb_index or before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * slbmte here or the allocation bitmaps could get out of whack with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * the SLB.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * User SLB faults or preloads take this path which might get inlined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * into the caller, so add compiler barriers here to ensure unsafe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * memory accesses do not come between.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) index = alloc_slb_index(kernel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) vsid_data = __mk_vsid_data(vsid, ssize, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) esid_data = mk_esid_data(ea, ssize, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * No need for an isync before or after this slbmte. The exception
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * we enter with and the rfid we exit with are context synchronizing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * User preloads should add isync afterwards in case the kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * accesses user memory before it returns to userspace with rfid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) assert_slb_presence(false, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (stress_slb()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int slb_cache_index = local_paca->slb_cache_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * stress_slb() does not use slb cache, repurpose as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * cache of inserted (non-bolted) kernel SLB entries. All
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * non-bolted kernel entries are flushed on any user fault,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * or if there are already 3 non-boled kernel entries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) BUILD_BUG_ON(SLB_CACHE_ENTRIES < 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!kernel || slb_cache_index == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) for (i = 0; i < slb_cache_index; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) slb_cache_slbie_kernel(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) slb_cache_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) local_paca->slb_cache[slb_cache_index++] = esid_data >> SID_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) local_paca->slb_cache_ptr = slb_cache_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) asm volatile("slbmte %0, %1" : : "r" (vsid_data), "r" (esid_data));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (!kernel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) slb_cache_update(esid_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static long slb_allocate_kernel(unsigned long ea, unsigned long id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned long context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ssize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (id == LINEAR_MAP_REGION_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /* We only support upto H_MAX_PHYSMEM_BITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if ((ea & EA_MASK) > (1UL << H_MAX_PHYSMEM_BITS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #ifdef CONFIG_SPARSEMEM_VMEMMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else if (id == VMEMMAP_REGION_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (ea >= H_VMEMMAP_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_vmemmap_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else if (id == VMALLOC_REGION_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (ea >= H_VMALLOC_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) flags = local_paca->vmalloc_sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else if (id == IO_REGION_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (ea >= H_KERN_IO_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) flags = SLB_VSID_KERNEL | mmu_psize_defs[mmu_io_psize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) ssize = MMU_SEGSIZE_1T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!mmu_has_feature(MMU_FTR_1T_SEGMENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ssize = MMU_SEGSIZE_256M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) context = get_kernel_context(ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return slb_insert_entry(ea, context, flags, ssize, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static long slb_allocate_user(struct mm_struct *mm, unsigned long ea)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned long context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int bpsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int ssize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) * consider this as bad access if we take a SLB miss
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * on an address above addr limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ea >= mm_ctx_slb_addr_limit(&mm->context))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) context = get_user_context(&mm->context, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (!context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (unlikely(ea >= H_PGTABLE_RANGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ssize = user_segment_size(ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) bpsize = get_slice_psize(mm, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) flags = SLB_VSID_USER | mmu_psize_defs[bpsize].sllp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return slb_insert_entry(ea, context, flags, ssize, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) long do_slb_fault(struct pt_regs *regs, unsigned long ea)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned long id = get_region_id(ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* IRQs are not reconciled here, so can't check irqs_disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) VM_WARN_ON(mfmsr() & MSR_EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (unlikely(!(regs->msr & MSR_RI)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * SLB kernel faults must be very careful not to touch anything
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * that is not bolted. E.g., PACA and global variables are okay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * mm->context stuff is not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * SLB user faults can access all of kernel memory, but must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * careful not to touch things like IRQ state because it is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * "reconciled" here. The difficulty is that we must use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) * fast_exception_return to return from kernel SLB faults without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * looking at possible non-bolted memory. We could test user vs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * kernel faults in the interrupt handler asm and do a full fault,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * reconcile, ret_from_except for user faults which would make them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * first class kernel code. But for performance it's probably nicer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * if they go via fast_exception_return too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (id >= LINEAR_MAP_REGION_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) long err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #ifdef CONFIG_DEBUG_VM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Catch recursive kernel SLB faults. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) BUG_ON(local_paca->in_kernel_slb_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) local_paca->in_kernel_slb_handler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) err = slb_allocate_kernel(ea, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #ifdef CONFIG_DEBUG_VM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) local_paca->in_kernel_slb_handler = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct mm_struct *mm = current->mm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) long err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (unlikely(!mm))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) err = slb_allocate_user(mm, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) preload_add(current_thread_info(), ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) void do_bad_slb_fault(struct pt_regs *regs, unsigned long ea, long err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (err == -EFAULT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (user_mode(regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) _exception(SIGSEGV, regs, SEGV_BNDERR, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) bad_page_fault(regs, ea, SIGSEGV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) } else if (err == -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) unrecoverable_exception(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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