^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This file contains the routines for handling the MMU on those
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * PowerPC implementations where the MMU substantially follows the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * architecture specification. This includes the 6xx, 7xx, 7xxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * and 8260 implementations but excludes the 8xx and 4xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * -- paulus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Derived from arch/ppc/mm/init.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * and Cort Dougan (PReP) (cort@cs.nmt.edu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1996 Paul Mackerras
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Derived from "arch/i386/mm/init.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/memblock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/code-patching.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/sections.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <mm/mmu_decl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct hash_pte *Hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static unsigned long Hash_size, Hash_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned long _SDR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static unsigned int hash_mb, hash_mb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct ppc_bat BATS[8][2]; /* 8 pairs of IBAT, DBAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct batrange { /* stores address ranges mapped by BATs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned long start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned long limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) phys_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) } bat_addrs[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Return PA for this VA if it is mapped by a BAT, or 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) phys_addr_t v_block_mapped(unsigned long va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return bat_addrs[b].phys + (va - bat_addrs[b].start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * Return VA for a given PA or 0 if not mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned long p_block_mapped(phys_addr_t pa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (pa >= bat_addrs[b].phys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) && pa < (bat_addrs[b].limit-bat_addrs[b].start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) +bat_addrs[b].phys)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return bat_addrs[b].start+(pa-bat_addrs[b].phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int __init find_free_bat(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (b = 0; b < n; b++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct ppc_bat *bat = BATS[b];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (!(bat[1].batu & 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * This function calculates the size of the larger block usable to map the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * beginning of an area based on the start address and size of that area:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * - max block size is 256 on 6xx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * - base address must be aligned to the block size. So the maximum block size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * is identified by the lowest bit set to 1 in the base address (for instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * if base is 0x16000000, max size is 0x02000000).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * - block size has to be a power of two. This is calculated by finding the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * highest bit set to 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int bat_block_size(unsigned long base, unsigned long top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int max_size = SZ_256M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int base_shift = (ffs(base) - 1) & 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int block_shift = (fls(top - base) - 1) & 31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) return min3(max_size, 1U << base_shift, 1U << block_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * Set up one of the IBAT (block address translation) register pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * The parameters are not checked; in particular size must be a power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * of 2 between 128k and 256M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void setibat(int index, unsigned long virt, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int size, pgprot_t prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int bl = (size >> 17) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int wimgxpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct ppc_bat *bat = BATS[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long flags = pgprot_val(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (!cpu_has_feature(CPU_FTR_NEED_COHERENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) flags &= ~_PAGE_COHERENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) wimgxpp = (flags & _PAGE_COHERENT) | (_PAGE_EXEC ? BPP_RX : BPP_XX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (flags & _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bat[0].batu |= 1; /* Vp = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static void clearibat(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ppc_bat *bat = BATS[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bat[0].batu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bat[0].batl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) while ((idx = find_free_bat()) != -1 && base != top) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int size = bat_block_size(base, top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (size < 128 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) base += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (__map_without_bats) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) pr_debug("RAM mapped without BATs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (debug_pagealloc_enabled()) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) if (base >= border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (top >= border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) top = border;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (!strict_kernel_rwx_enabled() || base >= border || top <= border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return __mmu_mapin_ram(base, top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) done = __mmu_mapin_ram(base, border);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (done != border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return __mmu_mapin_ram(border, top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static bool is_module_segment(unsigned long addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (!IS_ENABLED(CONFIG_MODULES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #ifdef MODULES_VADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (addr < ALIGN_DOWN(MODULES_VADDR, SZ_256M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (addr > ALIGN(MODULES_END, SZ_256M) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (addr < ALIGN_DOWN(VMALLOC_START, SZ_256M))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (addr > ALIGN(VMALLOC_END, SZ_256M) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) void mmu_mark_initmem_nx(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long top = ALIGN((unsigned long)_etext - PAGE_OFFSET, SZ_128K);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) unsigned long size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i = 0; i < nb - 1 && base < top;) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) size = bat_block_size(base, top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) base += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (base < top) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) size = bat_block_size(base, top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if ((top - base) > size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) size <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (strict_kernel_rwx_enabled() && base + size > border)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) pr_warn("Some RW data is getting mapped X. "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "Adjust CONFIG_DATA_SHIFT to avoid that.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) base += size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) for (; i < nb; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) clearibat(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) update_bats();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) for (i = TASK_SIZE >> 28; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Do not set NX on VM space for modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (is_module_segment(i << 28))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mtsrin(mfsrin(i << 28) | 0x10000000, i << 28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) void mmu_mark_rodata_ro(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) for (i = 0; i < nb; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ppc_bat *bat = BATS[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (bat_addrs[i].start < (unsigned long)__init_begin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) update_bats();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * Set up one of the I/D BAT (block address translation) register pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * The parameters are not checked; in particular size must be a power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * of 2 between 128k and 256M.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * On 603+, only set IBAT when _PAGE_EXEC is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void __init setbat(int index, unsigned long virt, phys_addr_t phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) unsigned int size, pgprot_t prot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int bl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int wimgxpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct ppc_bat *bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) unsigned long flags = pgprot_val(prot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (index == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) index = find_free_bat();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (index == -1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) pr_err("%s: no BAT available for mapping 0x%llx\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) (unsigned long long)phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) bat = BATS[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if ((flags & _PAGE_NO_CACHE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) flags &= ~_PAGE_COHERENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) bl = (size >> 17) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Do DBAT first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) | _PAGE_COHERENT | _PAGE_GUARDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (flags & _PAGE_USER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) bat[1].batu |= 1; /* Vp = 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (flags & _PAGE_GUARDED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* G bit must be zero in IBATs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) flags &= ~_PAGE_EXEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (flags & _PAGE_EXEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) bat[0] = bat[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) bat[0].batu = bat[0].batl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) bat_addrs[index].start = virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) bat_addrs[index].phys = phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * Preload a translation in the hash table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) void hash_preload(struct mm_struct *mm, unsigned long ea)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) pmd_t *pmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (!Hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) pmd = pmd_off(mm, ea);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!pmd_none(*pmd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) add_hash_page(mm->context.id, ea, pmd_val(*pmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * This is called at the end of handling a user page fault, when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * fault has been handled by updating a PTE in the linux page tables.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * We use it to preload an HPTE into the hash table corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * the updated linux PTE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * This must always be called with the pte lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) pte_t *ptep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * We don't need to worry about _PAGE_PRESENT here because we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * called with either mm->page_table_lock held or ptl lock held
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!pte_young(*ptep) || address >= TASK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* We have to test for regs NULL since init will get here first thing at boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (!current->thread.regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* We also avoid filling the hash if not coming from a fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (TRAP(current->thread.regs) != 0x300 && TRAP(current->thread.regs) != 0x400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) hash_preload(vma->vm_mm, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * Initialize the hash table and patch the instructions in hashtable.S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) void __init MMU_init_hw(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) unsigned int n_hpteg, lg_n_hpteg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MIN_N_HPTEG 1024 /* min 64kB hash table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * This is less than the recommended amount, but then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * Linux ain't AIX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) n_hpteg = total_memory / (PAGE_SIZE * 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (n_hpteg < MIN_N_HPTEG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) n_hpteg = MIN_N_HPTEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) lg_n_hpteg = __ilog2(n_hpteg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (n_hpteg & (n_hpteg - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ++lg_n_hpteg; /* round up if not power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) n_hpteg = 1 << lg_n_hpteg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) Hash_size = n_hpteg << LG_HPTEG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * Find some memory for the hash table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) Hash = memblock_alloc(Hash_size, Hash_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (!Hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __func__, Hash_size, Hash_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) pr_info("Total memory = %lldMB; using %ldkB for hash table\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) (unsigned long long)(total_memory >> 20), Hash_size >> 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) Hash_mask = n_hpteg - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) hash_mb2 = hash_mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (lg_n_hpteg > 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) hash_mb2 = 16 - LG_HPTEG_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) void __init MMU_init_hw_patch(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int hash = (unsigned int)Hash - PAGE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ppc_md.progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ppc_md.progress("hash:patch", 0x345);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ppc_md.progress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ppc_md.progress("hash:done", 0x205);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* WARNING: Make sure nothing can trigger a KASAN check past this point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Patch up the instructions in hashtable.S:create_hpte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) modify_instruction_site(&patch__hash_page_A1, 0x7c0, hash_mb << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) modify_instruction_site(&patch__hash_page_A2, 0x7c0, hash_mb2 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Patch up the instructions in hashtable.S:flush_hash_page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) modify_instruction_site(&patch__flush_hash_A1, 0x7c0, hash_mb << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) modify_instruction_site(&patch__flush_hash_A2, 0x7c0, hash_mb2 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) void setup_initial_memory_limit(phys_addr_t first_memblock_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) phys_addr_t first_memblock_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* We don't currently support the first MEMBLOCK not mapping 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * physical on those processors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) BUG_ON(first_memblock_base != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_256M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) void __init print_system_hash_info(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pr_info("Hash_size = 0x%lx\n", Hash_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (Hash_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) pr_info("Hash_mask = 0x%lx\n", Hash_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #ifdef CONFIG_PPC_KUEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) void __init setup_kuep(bool disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) pr_info("Activating Kernel Userspace Execution Prevention\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) pr_warn("KUEP cannot be disabled yet on 6xx when compiled in\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #ifdef CONFIG_PPC_KUAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) void __init setup_kuap(bool disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) pr_info("Activating Kernel Userspace Access Protection\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (disabled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) pr_warn("KUAP cannot be disabled yet on 6xx when compiled in\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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