Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #include <asm/sfp-machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #include <math-emu/soft-fp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) mtfsf(unsigned int FM, u32 *frB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	u32 fpscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	if (likely(FM == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		mask = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	else if (likely(FM == 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		mask = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		mask = ((FM & 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 				((FM << 3) & 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 				((FM << 6) & 0x100) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 				((FM << 9) & 0x1000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 				((FM << 12) & 0x10000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 				((FM << 15) & 0x100000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 				((FM << 18) & 0x1000000) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 				((FM << 21) & 0x10000000)) * 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	fpscr = ((__FPU_FPSCR & ~mask) | (frB[1] & mask)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		~(FPSCR_VX | FPSCR_FEX | 0x800);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	if (fpscr & (FPSCR_VXSNAN | FPSCR_VXISI | FPSCR_VXIDI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		     FPSCR_VXZDZ | FPSCR_VXIMZ | FPSCR_VXVC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		     FPSCR_VXSOFT | FPSCR_VXSQRT | FPSCR_VXCVI))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		fpscr |= FPSCR_VX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	/* The bit order of exception enables and exception status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	 * is the same. Simply shift and mask to check for enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	 * exceptions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	if (fpscr & (fpscr >> 22) &  0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		fpscr |= FPSCR_FEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	__FPU_FPSCR = fpscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	printk("%s: %02x %p: %08lx\n", __func__, FM, frB, __FPU_FPSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }