Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Floating-point, VMX/Altivec and VSX loads and stores
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * for use in instruction emulation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Copyright 2010 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/ppc-opcode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/asm-compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define STKFRM	(PPC_MIN_STKFRM + 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* Get the contents of frN into *p; N is in r3 and p is in r4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) _GLOBAL(get_fpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	ori	r7, r6, MSR_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	rlwinm	r3,r3,3,0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	bcl	20,31,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) reg = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	.rept	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	stfd	reg, 0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	b	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) reg = reg + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	add	r5,r3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	mtctr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 2:	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Put the contents of *p into frN; N is in r3 and p is in r4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) _GLOBAL(put_fpr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	ori	r7, r6, MSR_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	rlwinm	r3,r3,3,0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	bcl	20,31,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) reg = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.rept	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	lfd	reg, 0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	b	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) reg = reg + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	add	r5,r3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mtctr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 2:	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* Get the contents of vrN into *p; N is in r3 and p is in r4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) _GLOBAL(get_vr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	oris	r7, r6, MSR_VEC@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	rlwinm	r3,r3,3,0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	bcl	20,31,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) reg = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	.rept	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	stvx	reg, 0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	b	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) reg = reg + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	add	r5,r3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	mtctr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 2:	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Put the contents of *p into vrN; N is in r3 and p is in r4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) _GLOBAL(put_vr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	oris	r7, r6, MSR_VEC@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	rlwinm	r3,r3,3,0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	bcl	20,31,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.rept	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	lvx	reg, 0, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	b	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) reg = reg + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	add	r5,r3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	mtctr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 2:	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif /* CONFIG_ALTIVEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #ifdef CONFIG_VSX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Get the contents of vsN into vs0; N is in r3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) _GLOBAL(get_vsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	rlwinm	r3,r3,3,0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	bcl	20,31,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	blr			/* vs0 is already in vs0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) reg = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.rept	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	XXLOR(0,reg,reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) reg = reg + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	add	r5,r3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	mtctr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Put the contents of vs0 into vsN; N is in r3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) _GLOBAL(put_vsr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	rlwinm	r3,r3,3,0x1f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	bcl	20,31,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	blr			/* v0 is already in v0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) reg = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.rept	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	XXLOR(reg,0,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) reg = reg + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.endr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 1:	mflr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	add	r5,r3,r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mtctr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	bctr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* Load VSX reg N from vector doubleword *p.  N is in r3, p in r4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) _GLOBAL(load_vsrn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	PPC_STLU r1,-STKFRM(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	oris	r7,r6,MSR_VSX@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	cmpwi	cr7,r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	li	r8,STKFRM-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	beq	cr7,1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	STXVD2X(0,R1,R8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 1:	LXVD2X(0,R0,R4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #ifdef __LITTLE_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	XXSWAPD(0,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	beq	cr7,4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	bl	put_vsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	LXVD2X(0,R1,R8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 4:	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	addi	r1,r1,STKFRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Store VSX reg N to vector doubleword *p.  N is in r3, p in r4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) _GLOBAL(store_vsrn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	PPC_STLU r1,-STKFRM(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	PPC_STL	r0,STKFRM+PPC_LR_STKOFF(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	oris	r7,r6,MSR_VSX@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	li	r8,STKFRM-16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	STXVD2X(0,R1,R8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	bl	get_vsr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #ifdef __LITTLE_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	XXSWAPD(0,0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	STXVD2X(0,R0,R4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	LXVD2X(0,R1,R8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	PPC_LL	r0,STKFRM+PPC_LR_STKOFF(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mr	r3,r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	addi	r1,r1,STKFRM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* CONFIG_VSX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* Convert single-precision to double, without disturbing FPRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* conv_sp_to_dp(float *sp, double *dp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) _GLOBAL(conv_sp_to_dp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ori	r7, r6, MSR_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	stfd	fr0, -16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	lfs	fr0, 0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	stfd	fr0, 0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	lfd	fr0, -16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Convert single-precision to double, without disturbing FPRs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* conv_sp_to_dp(double *dp, float *sp) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) _GLOBAL(conv_dp_to_sp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	mfmsr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	ori	r7, r6, MSR_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	MTMSRD(r7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	stfd	fr0, -16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	lfd	fr0, 0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	stfs	fr0, 0(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	lfd	fr0, -16(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	MTMSRD(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	blr