^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright IBM Corp. 2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Authors: Hollis Blanchard <hollisb@us.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kvm_host.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/disassemble.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "booke.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OP_19_XOP_RFI 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OP_19_XOP_RFCI 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OP_19_XOP_RFDI 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OP_31_XOP_MFMSR 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OP_31_XOP_WRTEE 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OP_31_XOP_MTMSR 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OP_31_XOP_WRTEEI 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) vcpu->arch.regs.nip = vcpu->arch.dsrr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) vcpu->arch.regs.nip = vcpu->arch.csrr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int kvmppc_booke_emulate_op(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) unsigned int inst, int *advance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int rs = get_rs(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int rt = get_rt(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) switch (get_op(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) case 19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) switch (get_xop(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) case OP_19_XOP_RFI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) kvmppc_emul_rfi(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *advance = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) case OP_19_XOP_RFCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) kvmppc_emul_rfci(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *advance = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) case OP_19_XOP_RFDI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) kvmppc_emul_rfdi(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *advance = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (get_xop(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) case OP_31_XOP_MFMSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) case OP_31_XOP_MTMSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case OP_31_XOP_WRTEE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case OP_31_XOP_WRTEEI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) | (inst & MSR_EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return emulated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * Their backing store is in real registers, and these functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * will return the wrong result if called for them in another context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * (such as debugging).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool debug_inst = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) switch (sprn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case SPRN_DEAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) vcpu->arch.shared->dar = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case SPRN_ESR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) vcpu->arch.shared->esr = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) case SPRN_CSRR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) vcpu->arch.csrr0 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case SPRN_CSRR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) vcpu->arch.csrr1 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case SPRN_DSRR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) vcpu->arch.dsrr0 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) case SPRN_DSRR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) vcpu->arch.dsrr1 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) case SPRN_IAC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) vcpu->arch.dbg_reg.iac1 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case SPRN_IAC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vcpu->arch.dbg_reg.iac2 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #if CONFIG_PPC_ADV_DEBUG_IACS > 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) case SPRN_IAC3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) vcpu->arch.dbg_reg.iac3 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) case SPRN_IAC4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) vcpu->arch.dbg_reg.iac4 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case SPRN_DAC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) vcpu->arch.dbg_reg.dac1 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) case SPRN_DAC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) vcpu->arch.dbg_reg.dac2 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) case SPRN_DBCR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vcpu->arch.dbg_reg.dbcr0 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) case SPRN_DBCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) vcpu->arch.dbg_reg.dbcr1 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) case SPRN_DBCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) debug_inst = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vcpu->arch.dbg_reg.dbcr2 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case SPRN_DBSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * If userspace is debugging guest then guest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * can not access debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) vcpu->arch.dbsr &= ~spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!(vcpu->arch.dbsr & ~DBSR_IDE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) kvmppc_core_dequeue_debug(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case SPRN_TSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) kvmppc_clr_tsr_bits(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case SPRN_TCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * WRC is a 2-bit field that is supposed to preserve its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * value once written to non-zero.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (vcpu->arch.tcr & TCR_WRC_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) spr_val &= ~TCR_WRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) kvmppc_set_tcr(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case SPRN_DECAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) vcpu->arch.decar = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Note: SPRG4-7 are user-readable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * These values are loaded into the real SPRGs when resuming the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * guest (PR-mode only).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case SPRN_SPRG4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) kvmppc_set_sprg4(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) case SPRN_SPRG5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) kvmppc_set_sprg5(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case SPRN_SPRG6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) kvmppc_set_sprg6(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) case SPRN_SPRG7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) kvmppc_set_sprg7(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case SPRN_IVPR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) vcpu->arch.ivpr = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) mtspr(SPRN_GIVPR, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case SPRN_IVOR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case SPRN_IVOR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case SPRN_IVOR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mtspr(SPRN_GIVOR2, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case SPRN_IVOR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case SPRN_IVOR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case SPRN_IVOR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case SPRN_IVOR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case SPRN_IVOR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case SPRN_IVOR8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) mtspr(SPRN_GIVOR8, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case SPRN_IVOR9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case SPRN_IVOR10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case SPRN_IVOR11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case SPRN_IVOR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case SPRN_IVOR13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case SPRN_IVOR14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case SPRN_IVOR15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case SPRN_MCSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) vcpu->arch.mcsr &= ~spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #if defined(CONFIG_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case SPRN_EPCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) kvmppc_set_epcr(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #ifdef CONFIG_KVM_BOOKE_HV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (debug_inst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) current->thread.debug = vcpu->arch.dbg_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch_booke_debug_regs(&vcpu->arch.dbg_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return emulated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) switch (sprn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) case SPRN_IVPR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) *spr_val = vcpu->arch.ivpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) case SPRN_DEAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) *spr_val = vcpu->arch.shared->dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) case SPRN_ESR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) *spr_val = vcpu->arch.shared->esr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) case SPRN_EPR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) *spr_val = vcpu->arch.epr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case SPRN_CSRR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *spr_val = vcpu->arch.csrr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case SPRN_CSRR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) *spr_val = vcpu->arch.csrr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) case SPRN_DSRR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) *spr_val = vcpu->arch.dsrr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case SPRN_DSRR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) *spr_val = vcpu->arch.dsrr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case SPRN_IAC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) *spr_val = vcpu->arch.dbg_reg.iac1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) case SPRN_IAC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *spr_val = vcpu->arch.dbg_reg.iac2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #if CONFIG_PPC_ADV_DEBUG_IACS > 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case SPRN_IAC3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *spr_val = vcpu->arch.dbg_reg.iac3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case SPRN_IAC4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *spr_val = vcpu->arch.dbg_reg.iac4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case SPRN_DAC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *spr_val = vcpu->arch.dbg_reg.dac1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) case SPRN_DAC2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *spr_val = vcpu->arch.dbg_reg.dac2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case SPRN_DBCR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *spr_val = vcpu->arch.dbg_reg.dbcr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (vcpu->guest_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) *spr_val = *spr_val | DBCR0_EDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case SPRN_DBCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) *spr_val = vcpu->arch.dbg_reg.dbcr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case SPRN_DBCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *spr_val = vcpu->arch.dbg_reg.dbcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case SPRN_DBSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) *spr_val = vcpu->arch.dbsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case SPRN_TSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) *spr_val = vcpu->arch.tsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) case SPRN_TCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) *spr_val = vcpu->arch.tcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) case SPRN_IVOR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case SPRN_IVOR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) case SPRN_IVOR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case SPRN_IVOR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case SPRN_IVOR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case SPRN_IVOR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) case SPRN_IVOR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) case SPRN_IVOR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case SPRN_IVOR8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case SPRN_IVOR9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) case SPRN_IVOR10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) case SPRN_IVOR11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case SPRN_IVOR12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) case SPRN_IVOR13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) case SPRN_IVOR14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case SPRN_IVOR15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) case SPRN_MCSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *spr_val = vcpu->arch.mcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #if defined(CONFIG_64BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) case SPRN_EPCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *spr_val = vcpu->arch.epcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return emulated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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