^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright SUSE Linux Products GmbH 2009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Authors: Alexander Graf <agraf@suse.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/kvm_ppc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/disassemble.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/kvm_book3s.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/switch_to.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/time.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/tm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "book3s.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/asm-prototypes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OP_19_XOP_RFID 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OP_19_XOP_RFI 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OP_31_XOP_MFMSR 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OP_31_XOP_MTMSR 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OP_31_XOP_MTMSRD 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OP_31_XOP_MTSR 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OP_31_XOP_MTSRIN 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OP_31_XOP_TLBIEL 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Opcode is officially reserved, reuse it as sc 1 when sc 1 doesn't trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OP_31_XOP_FAKE_SC1 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OP_31_XOP_SLBMTE 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OP_31_XOP_SLBIE 434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OP_31_XOP_SLBIA 498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OP_31_XOP_MFSR 595
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OP_31_XOP_MFSRIN 659
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OP_31_XOP_DCBA 758
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OP_31_XOP_SLBMFEV 851
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OP_31_XOP_EIOIO 854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OP_31_XOP_SLBMFEE 915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OP_31_XOP_SLBFEE 979
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OP_31_XOP_TBEGIN 654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OP_31_XOP_TABORT 910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OP_31_XOP_TRECLAIM 942
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OP_31_XOP_TRCHKPT 1006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* DCBZ is actually 1014, but we patch it to 1010 so we get a trap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OP_31_XOP_DCBZ 1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OP_LFS 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OP_LFD 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OP_STFS 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OP_STFD 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPRN_GQR0 912
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPRN_GQR1 913
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPRN_GQR2 914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPRN_GQR3 915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPRN_GQR4 916
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPRN_GQR5 917
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SPRN_GQR6 918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPRN_GQR7 919
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Book3S_32 defines mfsrin(v) - but that messes up our abstract
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * function pointers, so let's just disable the define. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #undef mfsrin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) enum priv_level {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PRIV_PROBLEM = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) PRIV_SUPER = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) PRIV_HYPER = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static bool spr_allowed(struct kvm_vcpu *vcpu, enum priv_level level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* PAPR VMs only access supervisor SPRs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (vcpu->arch.papr_enabled && (level > PRIV_SUPER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Limit user space to its own small SPR set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if ((kvmppc_get_msr(vcpu) & MSR_PR) && level > PRIV_PROBLEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static inline void kvmppc_copyto_vcpu_tm(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) memcpy(&vcpu->arch.gpr_tm[0], &vcpu->arch.regs.gpr[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) sizeof(vcpu->arch.gpr_tm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) memcpy(&vcpu->arch.fp_tm, &vcpu->arch.fp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) sizeof(struct thread_fp_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) memcpy(&vcpu->arch.vr_tm, &vcpu->arch.vr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) sizeof(struct thread_vr_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) vcpu->arch.ppr_tm = vcpu->arch.ppr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) vcpu->arch.dscr_tm = vcpu->arch.dscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) vcpu->arch.amr_tm = vcpu->arch.amr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) vcpu->arch.ctr_tm = vcpu->arch.regs.ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) vcpu->arch.tar_tm = vcpu->arch.tar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) vcpu->arch.lr_tm = vcpu->arch.regs.link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) vcpu->arch.cr_tm = vcpu->arch.regs.ccr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) vcpu->arch.xer_tm = vcpu->arch.regs.xer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) vcpu->arch.vrsave_tm = vcpu->arch.vrsave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static inline void kvmppc_copyfrom_vcpu_tm(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) memcpy(&vcpu->arch.regs.gpr[0], &vcpu->arch.gpr_tm[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) sizeof(vcpu->arch.regs.gpr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) memcpy(&vcpu->arch.fp, &vcpu->arch.fp_tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) sizeof(struct thread_fp_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) memcpy(&vcpu->arch.vr, &vcpu->arch.vr_tm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) sizeof(struct thread_vr_state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) vcpu->arch.ppr = vcpu->arch.ppr_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) vcpu->arch.dscr = vcpu->arch.dscr_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) vcpu->arch.amr = vcpu->arch.amr_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) vcpu->arch.regs.ctr = vcpu->arch.ctr_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) vcpu->arch.tar = vcpu->arch.tar_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) vcpu->arch.regs.link = vcpu->arch.lr_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) vcpu->arch.regs.ccr = vcpu->arch.cr_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) vcpu->arch.regs.xer = vcpu->arch.xer_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) vcpu->arch.vrsave = vcpu->arch.vrsave_tm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void kvmppc_emulate_treclaim(struct kvm_vcpu *vcpu, int ra_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned long guest_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int fc_val = ra_val ? ra_val : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) uint64_t texasr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* CR0 = 0 | MSR[TS] | 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) (((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) << CR0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) tm_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) texasr = mfspr(SPRN_TEXASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) kvmppc_save_tm_pr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) kvmppc_copyfrom_vcpu_tm(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* failure recording depends on Failure Summary bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!(texasr & TEXASR_FS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) texasr &= ~TEXASR_FC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) texasr |= ((u64)fc_val << TEXASR_FC_LG) | TEXASR_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) texasr &= ~(TEXASR_PR | TEXASR_HV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (kvmppc_get_msr(vcpu) & MSR_PR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) texasr |= TEXASR_PR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (kvmppc_get_msr(vcpu) & MSR_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) texasr |= TEXASR_HV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) vcpu->arch.texasr = texasr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mtspr(SPRN_TEXASR, texasr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) mtspr(SPRN_TFIAR, vcpu->arch.tfiar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) tm_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * treclaim need quit to non-transactional state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) guest_msr &= ~(MSR_TS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) kvmppc_set_msr(vcpu, guest_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (vcpu->arch.shadow_fscr & FSCR_TAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) mtspr(SPRN_TAR, vcpu->arch.tar);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void kvmppc_emulate_trchkpt(struct kvm_vcpu *vcpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) unsigned long guest_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * need flush FP/VEC/VSX to vcpu save area before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * copy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) kvmppc_giveup_ext(vcpu, MSR_VSX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) kvmppc_giveup_fac(vcpu, FSCR_TAR_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) kvmppc_copyto_vcpu_tm(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) kvmppc_save_tm_sprs(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * as a result of trecheckpoint. set TS to suspended.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) guest_msr &= ~(MSR_TS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) guest_msr |= MSR_TS_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) kvmppc_set_msr(vcpu, guest_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) kvmppc_restore_tm_pr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* emulate tabort. at guest privilege state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* currently we only emulate tabort. but no emulation of other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * tabort variants since there is no kernel usage of them at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) unsigned long guest_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) uint64_t org_texasr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) tm_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) org_texasr = mfspr(SPRN_TEXASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tm_abort(ra_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* CR0 = 0 | MSR[TS] | 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (((guest_msr & MSR_TS_MASK) >> (MSR_TS_S_LG - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) << CR0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) vcpu->arch.texasr = mfspr(SPRN_TEXASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* failure recording depends on Failure Summary bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * and tabort will be treated as nops in non-transactional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (!(org_texasr & TEXASR_FS) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MSR_TM_ACTIVE(guest_msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vcpu->arch.texasr &= ~(TEXASR_PR | TEXASR_HV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (guest_msr & MSR_PR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vcpu->arch.texasr |= TEXASR_PR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (guest_msr & MSR_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vcpu->arch.texasr |= TEXASR_HV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) tm_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int kvmppc_core_emulate_op_pr(struct kvm_vcpu *vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned int inst, int *advance)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int rt = get_rt(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int rs = get_rs(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int ra = get_ra(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int rb = get_rb(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 inst_sc = 0x44000002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) switch (get_op(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if ((kvmppc_get_msr(vcpu) & MSR_LE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (inst == swab32(inst_sc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * This is the byte reversed syscall instruction of our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * hypercall handler. Early versions of LE Linux didn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * swap the instructions correctly and ended up in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * illegal instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * Just always fail hypercalls on these broken systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) kvmppc_set_gpr(vcpu, 3, EV_UNIMPLEMENTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) kvmppc_set_pc(vcpu, kvmppc_get_pc(vcpu) + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) case 19:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) switch (get_xop(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case OP_19_XOP_RFID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case OP_19_XOP_RFI: {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) unsigned long srr1 = kvmppc_get_srr1(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long cur_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * add rules to fit in ISA specification regarding TM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * state transistion in TM disable/Suspended state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * and target TM state is TM inactive(00) state. (the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * change should be suppressed).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (((cur_msr & MSR_TM) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ((srr1 & MSR_TM) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MSR_TM_SUSPENDED(cur_msr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) !MSR_TM_ACTIVE(srr1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) srr1 |= MSR_TS_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) kvmppc_set_pc(vcpu, kvmppc_get_srr0(vcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) kvmppc_set_msr(vcpu, srr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *advance = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) case 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) switch (get_xop(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case OP_31_XOP_MFMSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) kvmppc_set_gpr(vcpu, rt, kvmppc_get_msr(vcpu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case OP_31_XOP_MTMSRD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ulong rs_val = kvmppc_get_gpr(vcpu, rs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (inst & 0x10000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ulong new_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) new_msr &= ~(MSR_RI | MSR_EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) new_msr |= rs_val & (MSR_RI | MSR_EE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) kvmppc_set_msr_fast(vcpu, new_msr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) kvmppc_set_msr(vcpu, rs_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case OP_31_XOP_MTMSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case OP_31_XOP_MFSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int srnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) srnum = kvmppc_get_field(inst, 12 + 32, 15 + 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (vcpu->arch.mmu.mfsrin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) kvmppc_set_gpr(vcpu, rt, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) case OP_31_XOP_MFSRIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int srnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) srnum = (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (vcpu->arch.mmu.mfsrin) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) sr = vcpu->arch.mmu.mfsrin(vcpu, srnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) kvmppc_set_gpr(vcpu, rt, sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case OP_31_XOP_MTSR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) vcpu->arch.mmu.mtsrin(vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) (inst >> 16) & 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) kvmppc_get_gpr(vcpu, rs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case OP_31_XOP_MTSRIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) vcpu->arch.mmu.mtsrin(vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) (kvmppc_get_gpr(vcpu, rb) >> 28) & 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) kvmppc_get_gpr(vcpu, rs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) case OP_31_XOP_TLBIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case OP_31_XOP_TLBIEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bool large = (inst & 0x00200000) ? true : false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ulong addr = kvmppc_get_gpr(vcpu, rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) vcpu->arch.mmu.tlbie(vcpu, addr, large);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case OP_31_XOP_FAKE_SC1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* SC 1 papr hypercalls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ulong cmd = kvmppc_get_gpr(vcpu, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if ((kvmppc_get_msr(vcpu) & MSR_PR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) !vcpu->arch.papr_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) vcpu->run->papr_hcall.nr = cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) for (i = 0; i < 9; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ulong gpr = kvmppc_get_gpr(vcpu, 4 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) vcpu->run->papr_hcall.args[i] = gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) vcpu->run->exit_reason = KVM_EXIT_PAPR_HCALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) vcpu->arch.hcall_needed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) emulated = EMULATE_EXIT_USER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case OP_31_XOP_EIOIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) case OP_31_XOP_SLBMTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!vcpu->arch.mmu.slbmte)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) vcpu->arch.mmu.slbmte(vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) kvmppc_get_gpr(vcpu, rs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) kvmppc_get_gpr(vcpu, rb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case OP_31_XOP_SLBIE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (!vcpu->arch.mmu.slbie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) vcpu->arch.mmu.slbie(vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) kvmppc_get_gpr(vcpu, rb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case OP_31_XOP_SLBIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!vcpu->arch.mmu.slbia)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) vcpu->arch.mmu.slbia(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) case OP_31_XOP_SLBFEE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!(inst & 1) || !vcpu->arch.mmu.slbfee) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ulong b, t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ulong cr = kvmppc_get_cr(vcpu) & ~CR0_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) b = kvmppc_get_gpr(vcpu, rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (!vcpu->arch.mmu.slbfee(vcpu, b, &t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) cr |= 2 << CR0_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) kvmppc_set_gpr(vcpu, rt, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* copy XER[SO] bit to CR0[SO] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cr |= (vcpu->arch.regs.xer & 0x80000000) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) (31 - CR0_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) kvmppc_set_cr(vcpu, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case OP_31_XOP_SLBMFEE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (!vcpu->arch.mmu.slbmfee) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ulong t, rb_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rb_val = kvmppc_get_gpr(vcpu, rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) t = vcpu->arch.mmu.slbmfee(vcpu, rb_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) kvmppc_set_gpr(vcpu, rt, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case OP_31_XOP_SLBMFEV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!vcpu->arch.mmu.slbmfev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ulong t, rb_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rb_val = kvmppc_get_gpr(vcpu, rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) t = vcpu->arch.mmu.slbmfev(vcpu, rb_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) kvmppc_set_gpr(vcpu, rt, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) case OP_31_XOP_DCBA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Gets treated as NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) case OP_31_XOP_DCBZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ulong rb_val = kvmppc_get_gpr(vcpu, rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ulong ra_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ulong addr, vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 zeros[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ra_val = kvmppc_get_gpr(vcpu, ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) addr = (ra_val + rb_val) & ~31ULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (!(kvmppc_get_msr(vcpu) & MSR_SF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) addr &= 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) vaddr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) r = kvmppc_st(vcpu, &addr, 32, zeros, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if ((r == -ENOENT) || (r == -EPERM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) *advance = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) kvmppc_set_dar(vcpu, vaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) vcpu->arch.fault_dar = vaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dsisr = DSISR_ISSTORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (r == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dsisr |= DSISR_NOHPTE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) else if (r == -EPERM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dsisr |= DSISR_PROTFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) kvmppc_set_dsisr(vcpu, dsisr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) vcpu->arch.fault_dsisr = dsisr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) kvmppc_book3s_queue_irqprio(vcpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) BOOK3S_INTERRUPT_DATA_STORAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case OP_31_XOP_TBEGIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (!cpu_has_feature(CPU_FTR_TM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!(kvmppc_get_msr(vcpu) & MSR_PR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) preempt_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) vcpu->arch.regs.ccr = (CR0_TBEGIN_FAILURE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) (vcpu->arch.regs.ccr & ~(CR0_MASK << CR0_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) vcpu->arch.texasr = (TEXASR_FS | TEXASR_EXACT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) (((u64)(TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) << TEXASR_FC_LG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if ((inst >> 21) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) vcpu->arch.texasr |= TEXASR_ROT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (kvmppc_get_msr(vcpu) & MSR_HV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) vcpu->arch.texasr |= TEXASR_HV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) vcpu->arch.tfhar = kvmppc_get_pc(vcpu) + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) vcpu->arch.tfiar = kvmppc_get_pc(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) kvmppc_restore_tm_sprs(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) preempt_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) case OP_31_XOP_TABORT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ulong guest_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned long ra_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (!cpu_has_feature(CPU_FTR_TM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* only emulate for privilege guest, since problem state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * guest can run with TM enabled and we don't expect to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) * trap at here for that case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) WARN_ON(guest_msr & MSR_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ra_val = kvmppc_get_gpr(vcpu, ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) kvmppc_emulate_tabort(vcpu, ra_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case OP_31_XOP_TRECLAIM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ulong guest_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned long ra_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (!cpu_has_feature(CPU_FTR_TM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* generate interrupts based on priorities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (guest_msr & MSR_PR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Privileged Instruction type Program Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!MSR_TM_ACTIVE(guest_msr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* TM bad thing interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ra_val = kvmppc_get_gpr(vcpu, ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) kvmppc_emulate_treclaim(vcpu, ra_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case OP_31_XOP_TRCHKPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ulong guest_msr = kvmppc_get_msr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long texasr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!cpu_has_feature(CPU_FTR_TM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* generate interrupt based on priorities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (guest_msr & MSR_PR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* Privileged Instruction type Program Intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) tm_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) texasr = mfspr(SPRN_TEXASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tm_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (MSR_TM_ACTIVE(guest_msr) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) !(texasr & (TEXASR_FS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* TM bad thing interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) kvmppc_emulate_trchkpt(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) emulated = EMULATE_FAIL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (emulated == EMULATE_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) emulated = kvmppc_emulate_paired_single(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return emulated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) void kvmppc_set_bat(struct kvm_vcpu *vcpu, struct kvmppc_bat *bat, bool upper,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (upper) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Upper BAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 bl = (val >> 2) & 0x7ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) bat->bepi_mask = (~bl << 17);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) bat->bepi = val & 0xfffe0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bat->vs = (val & 2) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) bat->vp = (val & 1) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) bat->raw = (bat->raw & 0xffffffff00000000ULL) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Lower BAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) bat->brpn = val & 0xfffe0000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) bat->wimg = (val >> 3) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) bat->pp = val & 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) bat->raw = (bat->raw & 0x00000000ffffffffULL) | ((u64)val << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static struct kvmppc_bat *kvmppc_find_bat(struct kvm_vcpu *vcpu, int sprn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct kvmppc_bat *bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) switch (sprn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) case SPRN_IBAT0U ... SPRN_IBAT3L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) bat = &vcpu_book3s->ibat[(sprn - SPRN_IBAT0U) / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) case SPRN_IBAT4U ... SPRN_IBAT7L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) bat = &vcpu_book3s->ibat[4 + ((sprn - SPRN_IBAT4U) / 2)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) case SPRN_DBAT0U ... SPRN_DBAT3L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) bat = &vcpu_book3s->dbat[(sprn - SPRN_DBAT0U) / 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) case SPRN_DBAT4U ... SPRN_DBAT7L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) bat = &vcpu_book3s->dbat[4 + ((sprn - SPRN_DBAT4U) / 2)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return bat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int kvmppc_core_emulate_mtspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) switch (sprn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case SPRN_SDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!spr_allowed(vcpu, PRIV_HYPER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto unprivileged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) to_book3s(vcpu)->sdr1 = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case SPRN_DSISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) kvmppc_set_dsisr(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) case SPRN_DAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) kvmppc_set_dar(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case SPRN_HIOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) to_book3s(vcpu)->hior = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case SPRN_IBAT0U ... SPRN_IBAT3L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) case SPRN_IBAT4U ... SPRN_IBAT7L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case SPRN_DBAT0U ... SPRN_DBAT3L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case SPRN_DBAT4U ... SPRN_DBAT7L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) kvmppc_set_bat(vcpu, bat, !(sprn % 2), (u32)spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* BAT writes happen so rarely that we're ok to flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * everything here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) kvmppc_mmu_pte_flush(vcpu, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) kvmppc_mmu_flush_segments(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case SPRN_HID0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) to_book3s(vcpu)->hid[0] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) case SPRN_HID1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) to_book3s(vcpu)->hid[1] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) case SPRN_HID2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) to_book3s(vcpu)->hid[2] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case SPRN_HID2_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) to_book3s(vcpu)->hid[2] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* HID2.PSE controls paired single on gekko */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) switch (vcpu->arch.pvr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case 0x00080200: /* lonestar 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case 0x00088202: /* lonestar 2.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case 0x70000100: /* gekko 1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) case 0x00080100: /* gekko 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case 0x00083203: /* gekko 2.3a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) case 0x00083213: /* gekko 2.3b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) case 0x00083204: /* gekko 2.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) case 0x00087200: /* broadway */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (vcpu->arch.hflags & BOOK3S_HFLAG_NATIVE_PS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Native paired singles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) } else if (spr_val & (1 << 29)) { /* HID2.PSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) vcpu->arch.hflags |= BOOK3S_HFLAG_PAIRED_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) kvmppc_giveup_ext(vcpu, MSR_FP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) vcpu->arch.hflags &= ~BOOK3S_HFLAG_PAIRED_SINGLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) case SPRN_HID4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) case SPRN_HID4_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) to_book3s(vcpu)->hid[4] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case SPRN_HID5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) to_book3s(vcpu)->hid[5] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* guest HID5 set can change is_dcbz32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (mfmsr() & MSR_HV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) case SPRN_GQR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case SPRN_GQR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case SPRN_GQR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case SPRN_GQR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case SPRN_GQR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case SPRN_GQR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case SPRN_GQR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case SPRN_GQR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) to_book3s(vcpu)->gqr[sprn - SPRN_GQR0] = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case SPRN_FSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) kvmppc_set_fscr(vcpu, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) case SPRN_BESCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) vcpu->arch.bescr = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) case SPRN_EBBHR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) vcpu->arch.ebbhr = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case SPRN_EBBRR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) vcpu->arch.ebbrr = spr_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case SPRN_TFHAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case SPRN_TEXASR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case SPRN_TFIAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!cpu_has_feature(CPU_FTR_TM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (MSR_TM_ACTIVE(kvmppc_get_msr(vcpu)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) !((MSR_TM_SUSPENDED(kvmppc_get_msr(vcpu))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) (sprn == SPRN_TFHAR))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* it is illegal to mtspr() TM regs in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) * other than non-transactional state, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * the exception of TFHAR in suspend state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) kvmppc_core_queue_program(vcpu, SRR1_PROGTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) tm_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (sprn == SPRN_TFHAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mtspr(SPRN_TFHAR, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) else if (sprn == SPRN_TEXASR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mtspr(SPRN_TEXASR, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mtspr(SPRN_TFIAR, spr_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) tm_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case SPRN_ICTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case SPRN_THRM1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) case SPRN_THRM2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case SPRN_THRM3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case SPRN_CTRLF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) case SPRN_CTRLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) case SPRN_L2CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) case SPRN_DSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case SPRN_MMCR0_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) case SPRN_MMCR1_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) case SPRN_PMC1_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case SPRN_PMC2_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) case SPRN_PMC3_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case SPRN_PMC4_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case SPRN_WPAR_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) case SPRN_MSSSR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case SPRN_DABR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case SPRN_MMCRS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case SPRN_MMCRA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) case SPRN_MMCR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) case SPRN_MMCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case SPRN_MMCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) case SPRN_UMMCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) unprivileged:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pr_info_ratelimited("KVM: invalid SPR write: %d\n", sprn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (sprn & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (kvmppc_get_msr(vcpu) & MSR_PR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if ((kvmppc_get_msr(vcpu) & MSR_PR) || sprn == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return emulated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int kvmppc_core_emulate_mfspr_pr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) int emulated = EMULATE_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) switch (sprn) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) case SPRN_IBAT0U ... SPRN_IBAT3L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case SPRN_IBAT4U ... SPRN_IBAT7L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case SPRN_DBAT0U ... SPRN_DBAT3L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case SPRN_DBAT4U ... SPRN_DBAT7L:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct kvmppc_bat *bat = kvmppc_find_bat(vcpu, sprn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (sprn % 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) *spr_val = bat->raw >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) *spr_val = bat->raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case SPRN_SDR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (!spr_allowed(vcpu, PRIV_HYPER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) goto unprivileged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) *spr_val = to_book3s(vcpu)->sdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) case SPRN_DSISR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) *spr_val = kvmppc_get_dsisr(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case SPRN_DAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) *spr_val = kvmppc_get_dar(vcpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) case SPRN_HIOR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) *spr_val = to_book3s(vcpu)->hior;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) case SPRN_HID0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) *spr_val = to_book3s(vcpu)->hid[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case SPRN_HID1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) *spr_val = to_book3s(vcpu)->hid[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case SPRN_HID2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) case SPRN_HID2_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) *spr_val = to_book3s(vcpu)->hid[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) case SPRN_HID4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) case SPRN_HID4_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) *spr_val = to_book3s(vcpu)->hid[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) case SPRN_HID5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) *spr_val = to_book3s(vcpu)->hid[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case SPRN_CFAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) case SPRN_DSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) *spr_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case SPRN_PURR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * On exit we would have updated purr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) *spr_val = vcpu->arch.purr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case SPRN_SPURR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * On exit we would have updated spurr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) *spr_val = vcpu->arch.spurr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) case SPRN_VTB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) *spr_val = to_book3s(vcpu)->vtb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case SPRN_IC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) *spr_val = vcpu->arch.ic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case SPRN_GQR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case SPRN_GQR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case SPRN_GQR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) case SPRN_GQR3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case SPRN_GQR4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case SPRN_GQR5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) case SPRN_GQR6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) case SPRN_GQR7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) *spr_val = to_book3s(vcpu)->gqr[sprn - SPRN_GQR0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case SPRN_FSCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) *spr_val = vcpu->arch.fscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) case SPRN_BESCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *spr_val = vcpu->arch.bescr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case SPRN_EBBHR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) *spr_val = vcpu->arch.ebbhr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case SPRN_EBBRR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) *spr_val = vcpu->arch.ebbrr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case SPRN_TFHAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case SPRN_TEXASR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case SPRN_TFIAR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!cpu_has_feature(CPU_FTR_TM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (!(kvmppc_get_msr(vcpu) & MSR_TM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) kvmppc_trigger_fac_interrupt(vcpu, FSCR_TM_LG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) tm_enable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (sprn == SPRN_TFHAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) *spr_val = mfspr(SPRN_TFHAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) else if (sprn == SPRN_TEXASR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) *spr_val = mfspr(SPRN_TEXASR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) else if (sprn == SPRN_TFIAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *spr_val = mfspr(SPRN_TFIAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) tm_disable();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) case SPRN_THRM1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) case SPRN_THRM2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) case SPRN_THRM3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) case SPRN_CTRLF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) case SPRN_CTRLT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case SPRN_L2CR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case SPRN_MMCR0_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case SPRN_MMCR1_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case SPRN_PMC1_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case SPRN_PMC2_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case SPRN_PMC3_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) case SPRN_PMC4_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) case SPRN_WPAR_GEKKO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case SPRN_MSSSR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) case SPRN_DABR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case SPRN_MMCRS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case SPRN_MMCRA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case SPRN_MMCR0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) case SPRN_MMCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) case SPRN_MMCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) case SPRN_UMMCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case SPRN_TIR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) *spr_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unprivileged:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pr_info_ratelimited("KVM: invalid SPR read: %d\n", sprn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (sprn & 0x10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (kvmppc_get_msr(vcpu) & MSR_PR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) kvmppc_core_queue_program(vcpu, SRR1_PROGPRIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if ((kvmppc_get_msr(vcpu) & MSR_PR) || sprn == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sprn == 4 || sprn == 5 || sprn == 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) emulated = EMULATE_AGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return emulated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) u32 kvmppc_alignment_dsisr(struct kvm_vcpu *vcpu, unsigned int inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return make_dsisr(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ulong kvmppc_alignment_dar(struct kvm_vcpu *vcpu, unsigned int inst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) * Linux's fix_alignment() assumes that DAR is valid, so can we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return vcpu->arch.fault_dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ulong dar = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ulong ra = get_ra(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ulong rb = get_rb(inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) switch (get_op(inst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) case OP_LFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case OP_LFD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) case OP_STFD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) case OP_STFS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) dar = kvmppc_get_gpr(vcpu, ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) dar += (s32)((s16)inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) case 31:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dar = kvmppc_get_gpr(vcpu, ra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dar += kvmppc_get_gpr(vcpu, rb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) printk(KERN_INFO "KVM: Unaligned instruction 0x%x\n", inst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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