Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This file contains kexec low-level functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2002-2003 Eric Biederman  <ebiederm@xmission.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * PPC44x port. Copyright (C) 2011,  IBM Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * 		Author: Suzuki Poulose <suzuki@in.ibm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/kexec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 	.text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	 * Must be relocatable PIC code callable as a C function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	.globl relocate_new_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) relocate_new_kernel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	/* r3 = page_list   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	/* r4 = reboot_code_buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	/* r5 = start_address      */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #ifdef CONFIG_FSL_BOOKE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	mr	r29, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	mr	r30, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	mr	r31, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define ENTRY_MAPPING_KEXEC_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <kernel/fsl_booke_entry_mapping.S>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #undef ENTRY_MAPPING_KEXEC_SETUP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	mr      r3, r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	mr      r4, r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	mr      r5, r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	li	r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #elif defined(CONFIG_44x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	/* Save our parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	mr	r29, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	mr	r30, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	mr	r31, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #ifdef CONFIG_PPC_47x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	/* Check for 47x cores */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	mfspr	r3,SPRN_PVR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	srwi	r3,r3,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	cmplwi	cr0,r3,PVR_476FPE@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	beq	setup_map_47x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	cmplwi	cr0,r3,PVR_476@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	beq	setup_map_47x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	cmplwi	cr0,r3,PVR_476_ISS@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	beq	setup_map_47x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #endif /* CONFIG_PPC_47x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63)  * Code for setting up 1:1 mapping for PPC440x for KEXEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65)  * We cannot switch off the MMU on PPC44x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66)  * So we:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67)  * 1) Invalidate all the mappings except the one we are running from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68)  * 2) Create a tmp mapping for our code in the other address space(TS) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  *    jump to it. Invalidate the entry we started in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * 4) Jump to the 1:1 mapping in original TS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  * 5) Invalidate the tmp mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74)  * - Based on the kexec support code for FSL BookE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * Load the PID with kernel PID (0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * Also load our MSR_IS and TID to MMUCR for TLB search.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	mtspr	SPRN_PID, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mfmsr	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	andi.	r4,r4,MSR_IS@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	beq	wmmucr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	oris	r3,r3,PPC44x_MMUCR_STS@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) wmmucr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	mtspr	SPRN_MMUCR,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * Invalidate all the TLB entries except the current entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * where we are running from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	bl	0f				/* Find our address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 0:	mflr	r5				/* Make it accessible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	tlbsx	r23,0,r5			/* Find entry we are in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	li	r4,0				/* Start at TLB entry 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	li	r3,0				/* Set PAGEID inval value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 1:	cmpw	r23,r4				/* Is this our entry? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	beq	skip				/* If so, skip the inval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	tlbwe	r3,r4,PPC44x_TLB_PAGEID		/* If not, inval the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) skip:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	addi	r4,r4,1				/* Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	cmpwi	r4,64				/* Are we done?	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	bne	1b				/* If not, repeat */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	/* Create a temp mapping and jump to it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	andi.	r6, r23, 1		/* Find the index to use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	addi	r24, r6, 1		/* r24 will contain 1 or 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mfmsr	r9			/* get the MSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	rlwinm	r5, r9, 27, 31, 31	/* Extract the MSR[IS] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	xori	r7, r5, 1		/* Use the other address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* Read the current mapping entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	tlbre	r3, r23, PPC44x_TLB_PAGEID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	tlbre	r4, r23, PPC44x_TLB_XLAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	tlbre	r5, r23, PPC44x_TLB_ATTRIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Save our current XLAT entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	mr	r25, r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	/* Extract the TLB PageSize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	li	r10, 1 			/* r10 will hold PageSize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	rlwinm	r11, r3, 0, 24, 27	/* bits 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	/* XXX: As of now we use 256M, 4K pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	cmpwi	r11, PPC44x_TLB_256M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bne	tlb_4k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	rotlwi	r10, r10, 28		/* r10 = 256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	b	write_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tlb_4k:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	cmpwi	r11, PPC44x_TLB_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	bne	default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	rotlwi	r10, r10, 12		/* r10 = 4K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	b	write_out
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	rotlwi	r10, r10, 10		/* r10 = 1K */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) write_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 * Write out the tmp 1:1 mapping for this code in other address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	 * Fixup  EPN = RPN , TS=other address space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	insrwi	r3, r7, 1, 23		/* Bit 23 is TS for PAGEID field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	/* Write out the tmp mapping entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	tlbwe	r3, r24, PPC44x_TLB_PAGEID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	tlbwe	r4, r24, PPC44x_TLB_XLAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	tlbwe	r5, r24, PPC44x_TLB_ATTRIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	subi	r11, r10, 1		/* PageOffset Mask = PageSize - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	not	r10, r11		/* Mask for PageNum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	/* Switch to other address space in MSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	insrwi	r9, r7, 1, 26		/* Set MSR[IS] = r7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	bl	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 1:	mflr	r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	addi	r8, r8, (2f-1b)		/* Find the target offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	/* Jump to the tmp mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	mtspr	SPRN_SRR0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	mtspr	SPRN_SRR1, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* Invalidate the entry we were executing from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	tlbwe	r3, r23, PPC44x_TLB_PAGEID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	/* attribute fields. rwx for SUPERVISOR mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	li	r5, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ori	r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	/* Create 1:1 mapping in 256M pages */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	xori	r7, r7, 1			/* Revert back to Original TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	li	r8, 0				/* PageNumber */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	li	r6, 3				/* TLB Index, start at 3  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) next_tlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	rotlwi	r3, r8, 28			/* Create EPN (bits 0-3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	mr	r4, r3				/* RPN = EPN  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	ori	r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	insrwi	r3, r7, 1, 23			/* Set TS from r7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	tlbwe	r3, r6, PPC44x_TLB_PAGEID	/* PageID field : EPN, V, SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	tlbwe	r4, r6, PPC44x_TLB_XLAT		/* Address translation : RPN   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	tlbwe	r5, r6, PPC44x_TLB_ATTRIB	/* Attributes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	addi	r8, r8, 1			/* Increment PN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	addi	r6, r6, 1			/* Increment TLB Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	cmpwi	r8, 8				/* Are we done ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	bne	next_tlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	/* Jump to the new mapping 1:1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	li	r9,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	insrwi	r9, r7, 1, 26			/* Set MSR[IS] = r7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	bl	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 1:	mflr	r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	and	r8, r8, r11			/* Get our offset within page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	addi	r8, r8, (2f-1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	and	r5, r25, r10			/* Get our target PageNum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	or	r8, r8, r5			/* Target jump address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	mtspr	SPRN_SRR0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	mtspr	SPRN_SRR1, r9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	/* Invalidate the tmp entry we used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	tlbwe	r3, r24, PPC44x_TLB_PAGEID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	b	ppc44x_map_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #ifdef CONFIG_PPC_47x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	/* 1:1 mapping for 47x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) setup_map_47x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	 * Load the kernel pid (0) to PID and also to MMUCR[TID].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	 * Also set the MSR IS->MMUCR STS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	mtspr	SPRN_PID, r3			/* Set PID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mfmsr	r4				/* Get MSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	andi.	r4, r4, MSR_IS@l		/* TS=1? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	beq	1f				/* If not, leave STS=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	oris	r3, r3, PPC47x_MMUCR_STS@h	/* Set STS=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 1:	mtspr	SPRN_MMUCR, r3			/* Put MMUCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	/* Find the entry we are running from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	bl	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 2:	mflr	r23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	tlbsx	r23, 0, r23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	tlbre	r24, r23, 0			/* TLB Word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	tlbre	r25, r23, 1			/* TLB Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	tlbre	r26, r23, 2			/* TLB Word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	 * of 4k page size in all  4 ways (0-3 in r3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	 * This would invalidate the entire UTLB including the one we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	 * running from. However the shadow TLB entries would help us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	 * to continue the execution, until we flush them (rfi/isync).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	addis	r3, 0, 0x8000			/* specify the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	addi	r4, 0, 0			/* TLB Word0 = (EPN=0, VALID = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	addi	r5, 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	b	clear_utlb_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* Align the loop to speed things up. from head_44x.S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.align	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clear_utlb_entry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	tlbwe	r4, r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	tlbwe	r5, r3, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	tlbwe	r5, r3, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	addis	r3, r3, 0x2000			/* Increment the way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	cmpwi	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bne	clear_utlb_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	addis	r3, 0, 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	addis	r4, r4, 0x100			/* Increment the EPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	cmpwi	r4, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	bne	clear_utlb_entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/* Create the entries in the other address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	mfmsr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	rlwinm	r7, r5, 27, 31, 31		/* Get the TS (Bit 26) from MSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	xori	r7, r7, 1			/* r7 = !TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	insrwi	r24, r7, 1, 21			/* Change the TS in the saved TLB word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	 * write out the TLB entries for the tmp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	 * Use way '0' so that we could easily invalidate it later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	lis	r3, 0x8000			/* Way '0' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	tlbwe	r24, r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	tlbwe	r25, r3, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	tlbwe	r26, r3, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	/* Update the msr to the new TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	insrwi	r5, r7, 1, 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	bl	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 1:	mflr	r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	addi	r6, r6, (2f-1b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	mtspr	SPRN_SRR0, r6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mtspr	SPRN_SRR1, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	 * Now we are in the tmp address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	 * Create a 1:1 mapping for 0-2GiB in the original TS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	li	r4, 0				/* TLB Word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	li	r5, 0				/* TLB Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	li	r6, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	ori	r6, r6, PPC47x_TLB2_S_RWX	/* TLB word 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	li	r8, 0				/* PageIndex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	xori	r7, r7, 1			/* revert back to original TS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) write_utlb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	rotlwi	r5, r8, 28			/* RPN = PageIndex * 256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 						/* ERPN = 0 as we don't use memory above 2G */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	mr	r4, r5				/* EPN = RPN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	ori	r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	insrwi	r4, r7, 1, 21			/* Insert the TS to Word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	tlbwe	r4, r3, 0			/* Write out the entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	tlbwe	r5, r3, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	tlbwe	r6, r3, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	addi	r8, r8, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	cmpwi	r8, 8				/* Have we completed ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	bne	write_utlb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* make sure we complete the TLB write up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	 * Prepare to jump to the 1:1 mapping.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	 * 1) Extract page size of the tmp mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	 *    DSIZ = TLB_Word0[22:27]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	 * 2) Calculate the physical address of the address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	 *    to jump to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	rlwinm	r10, r24, 0, 22, 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	cmpwi	r10, PPC47x_TLB0_4K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	bne	0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	li	r10, 0x1000			/* r10 = 4k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	bl	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* Defaults to 256M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	lis	r10, 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	bl	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 1:	mflr	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	addi	r4, r4, (2f-1b)			/* virtual address  of 2f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	subi	r11, r10, 1			/* offsetmask = Pagesize - 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	not	r10, r11			/* Pagemask = ~(offsetmask) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	and	r5, r25, r10			/* Physical page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	and	r6, r4, r11			/* offset within the current page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	or	r5, r5, r6			/* Physical address for 2f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	/* Switch the TS in MSR to the original one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	mfmsr	r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	insrwi	r8, r7, 1, 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	mtspr	SPRN_SRR1, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	mtspr	SPRN_SRR0, r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	/* Invalidate the tmp mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	lis	r3, 0x8000			/* Way '0' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	clrrwi	r24, r24, 12			/* Clear the valid bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	tlbwe	r24, r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	tlbwe	r25, r3, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	tlbwe	r26, r3, 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	/* Make sure we complete the TLB write and flush the shadow TLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ppc44x_map_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	/* Restore the parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	mr	r3, r29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	mr	r4, r30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	mr	r5, r31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	li	r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	li	r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	 * Set Machine Status Register to a known status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	 * switch the MMU off and jump to 1: in a single step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	mr	r8, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	ori     r8, r8, MSR_RI|MSR_ME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	mtspr	SPRN_SRR1, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	addi	r8, r4, 1f - relocate_new_kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	mtspr	SPRN_SRR0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	/* from this point address translation is turned off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	/* and interrupts are disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	/* set a new stack at the bottom of our page... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	/* (not really needed now) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	addi	r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	stw	r0, 0(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	/* Do the copies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	li	r6, 0 /* checksum */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	mr	r0, r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	b	1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0:	/* top, read another word for the indirection page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	lwzu	r0, 4(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	/* is it a destination page? (r8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	rlwinm.	r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	beq	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	rlwinm	r8, r0, 0, 0, 19 /* clear kexec flags, page align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	b	0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 2:	/* is it an indirection page? (r3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	rlwinm.	r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	beq	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	rlwinm	r3, r0, 0, 0, 19 /* clear kexec flags, page align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	subi	r3, r3, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	b	0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 2:	/* are we done? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	rlwinm.	r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	beq	2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	b	3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 2:	/* is it a source page? (r9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	rlwinm.	r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	beq	0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	rlwinm	r9, r0, 0, 0, 19 /* clear kexec flags, page align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	li	r7, PAGE_SIZE / 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	mtctr   r7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	subi    r9, r9, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	subi    r8, r8, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	lwzu    r0, 4(r9)  /* do the copy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	xor	r6, r6, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	stwu    r0, 4(r8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	dcbst	0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	icbi	0, r8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	bdnz    9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	addi    r9, r9, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	addi    r8, r8, 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	b	0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	/* To be certain of avoiding problems with self-modifying code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	 * execute a serializing instruction here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	mfspr	r3, SPRN_PIR /* current core we are running on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	mr	r4, r5 /* load physical address of chunk called */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	/* jump to the entry point, usually the setup routine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	mtlr	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	blrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 1:	b	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) relocate_new_kernel_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	.globl relocate_new_kernel_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) relocate_new_kernel_size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	.long relocate_new_kernel_end - relocate_new_kernel