^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Signal trampoline for 64 bits processes in a ppc64 kernel for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * use in the vDSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/cache.h> /* IFETCH_ALIGN_BYTES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/vdso.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/ptrace.h> /* XXX for __SIGNAL_FRAMESIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * __kernel_start_sigtramp_rt64 and __kernel_sigtramp_rt64 together
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * are one function split in two parts. The kernel jumps to the former
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * and the signal handler indirectly (by blr) returns to the latter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * __kernel_sigtramp_rt64 needs to point to the return address so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * glibc can correctly identify the trampoline stack frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) .balign 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .balign IFETCH_ALIGN_BYTES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) V_FUNCTION_BEGIN(__kernel_start_sigtramp_rt64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) .Lsigrt_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) bctrl /* call the handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) V_FUNCTION_END(__kernel_start_sigtramp_rt64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) V_FUNCTION_BEGIN(__kernel_sigtramp_rt64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) addi r1, r1, __SIGNAL_FRAMESIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) li r0,__NR_rt_sigreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) sc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) .Lsigrt_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) V_FUNCTION_END(__kernel_sigtramp_rt64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* The .balign 8 above and the following zeros mimic the old stack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) trampoline layout. The last magic value is the ucontext pointer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) chosen in such a way that older libgcc unwind code returns a zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) for a sigcontext pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .long 0,0,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .quad 0,-21*8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Register r1 can be found at offset 8 of a pt_regs structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define cfa_save \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .byte 0x0f; /* DW_CFA_def_cfa_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Register REGNO can be found at offset OFS of a pt_regs structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define rsave(regno, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .uleb128 regno; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .ifne ofs; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .endif; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) of the VMX reg struct. A pointer to the VMX reg struct is at VREGS in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) the pt_regs struct. This macro is for REGNO == 0, and contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 'subroutines' that the other macros jump to. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define vsave_msr0(regno) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .byte 0x30 + regno; /* DW_OP_lit0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 2: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .byte 0x40; /* DW_OP_lit16 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .byte 0x1e; /* DW_OP_mul */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 3: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .byte 0x12; /* DW_OP_dup */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .byte 0x23; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .uleb128 33*RSIZE; /* msr offset */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .byte 0x1a; /* DW_OP_and */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .byte 0x30; /* DW_OP_lit0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .byte 0x29; /* DW_OP_eq */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .byte 0x13; /* DW_OP_drop, pop the 0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .byte 0x22; /* DW_OP_plus */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) of the VMX reg struct. REGNO is 1 thru 31. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define vsave_msr1(regno) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .byte 0x30 + regno; /* DW_OP_lit n */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) the VMX save block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define vsave_msr2(regno, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .byte 0x0a; .short ofs; /* DW_OP_const2u */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* VMX register REGNO is at offset OFS of the VMX save area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define vsave(regno, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* This is where the pt_regs pointer can be found on the stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PTREGS 128+168+56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Size of regs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define RSIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* Size of CR reg in DWARF unwind info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CRSIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Offset of CR reg within a full word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #ifdef __LITTLE_ENDIAN__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CROFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CROFF (RSIZE - CRSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* This is the offset of the VMX reg pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VREGS 48*RSIZE+33*8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Describe where general purpose regs are saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EH_FRAME_GEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) cfa_save; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rsave ( 0, 0*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rsave ( 2, 2*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rsave ( 3, 3*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rsave ( 4, 4*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rsave ( 5, 5*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rsave ( 6, 6*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rsave ( 7, 7*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rsave ( 8, 8*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rsave ( 9, 9*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) rsave (10, 10*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rsave (11, 11*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rsave (12, 12*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rsave (13, 13*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rsave (14, 14*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rsave (15, 15*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rsave (16, 16*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rsave (17, 17*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) rsave (18, 18*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) rsave (19, 19*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) rsave (20, 20*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rsave (21, 21*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) rsave (22, 22*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rsave (23, 23*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rsave (24, 24*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rsave (25, 25*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rsave (26, 26*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rsave (27, 27*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rsave (28, 28*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rsave (29, 29*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rsave (30, 30*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rsave (31, 31*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rsave (65, 36*RSIZE); /* lr */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rsave (68, 38*RSIZE + CROFF); /* cr fields */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rsave (69, 38*RSIZE + CROFF); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rsave (70, 38*RSIZE + CROFF); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rsave (71, 38*RSIZE + CROFF); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rsave (72, 38*RSIZE + CROFF); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rsave (73, 38*RSIZE + CROFF); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rsave (74, 38*RSIZE + CROFF); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rsave (75, 38*RSIZE + CROFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Describe where the FP regs are saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EH_FRAME_FP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rsave (32, 48*RSIZE + 0*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rsave (33, 48*RSIZE + 1*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rsave (34, 48*RSIZE + 2*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rsave (35, 48*RSIZE + 3*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rsave (36, 48*RSIZE + 4*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rsave (37, 48*RSIZE + 5*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rsave (38, 48*RSIZE + 6*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rsave (39, 48*RSIZE + 7*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) rsave (40, 48*RSIZE + 8*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) rsave (41, 48*RSIZE + 9*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) rsave (42, 48*RSIZE + 10*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) rsave (43, 48*RSIZE + 11*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rsave (44, 48*RSIZE + 12*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) rsave (45, 48*RSIZE + 13*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) rsave (46, 48*RSIZE + 14*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) rsave (47, 48*RSIZE + 15*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) rsave (48, 48*RSIZE + 16*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) rsave (49, 48*RSIZE + 17*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) rsave (50, 48*RSIZE + 18*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rsave (51, 48*RSIZE + 19*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) rsave (52, 48*RSIZE + 20*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) rsave (53, 48*RSIZE + 21*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) rsave (54, 48*RSIZE + 22*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) rsave (55, 48*RSIZE + 23*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) rsave (56, 48*RSIZE + 24*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) rsave (57, 48*RSIZE + 25*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) rsave (58, 48*RSIZE + 26*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) rsave (59, 48*RSIZE + 27*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) rsave (60, 48*RSIZE + 28*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rsave (61, 48*RSIZE + 29*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) rsave (62, 48*RSIZE + 30*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) rsave (63, 48*RSIZE + 31*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* Describe where the VMX regs are saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define EH_FRAME_VMX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) vsave_msr0 ( 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) vsave_msr1 ( 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vsave_msr1 ( 2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) vsave_msr1 ( 3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) vsave_msr1 ( 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) vsave_msr1 ( 5); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) vsave_msr1 ( 6); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vsave_msr1 ( 7); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) vsave_msr1 ( 8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) vsave_msr1 ( 9); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) vsave_msr1 (10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) vsave_msr1 (11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) vsave_msr1 (12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) vsave_msr1 (13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) vsave_msr1 (14); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) vsave_msr1 (15); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) vsave_msr1 (16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) vsave_msr1 (17); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) vsave_msr1 (18); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) vsave_msr1 (19); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) vsave_msr1 (20); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) vsave_msr1 (21); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) vsave_msr1 (22); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) vsave_msr1 (23); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) vsave_msr1 (24); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) vsave_msr1 (25); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) vsave_msr1 (26); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) vsave_msr1 (27); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) vsave_msr1 (28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) vsave_msr1 (29); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) vsave_msr1 (30); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) vsave_msr1 (31); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) vsave_msr2 (33, 32*16+12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) vsave (32, 33*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EH_FRAME_VMX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .section .eh_frame,"a",@progbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .Lcie:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .long .Lcie_end - .Lcie_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .Lcie_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .long 0 /* CIE ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .byte 1 /* Version number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .string "zRS" /* NUL-terminated augmentation string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .uleb128 4 /* Code alignment factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .sleb128 -8 /* Data alignment factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .byte 67 /* Return address register column, ap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .uleb128 1 /* Augmentation value length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .byte 0x14 /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .balign 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .Lcie_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .long .Lfde0_end - .Lfde0_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .Lfde0_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .long .Lfde0_start - .Lcie /* CIE pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .quad .Lsigrt_start - . /* PC start, length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .quad .Lsigrt_end - .Lsigrt_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .uleb128 0 /* Augmentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EH_FRAME_GEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EH_FRAME_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EH_FRAME_VMX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) # Do we really need to describe the frame at this point? ie. will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) # we ever have some call chain that returns somewhere past the addi?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) # I don't think so, since gcc doesn't support async signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) # .byte 0x41 /* DW_CFA_advance_loc 1*4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #undef PTREGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PTREGS 168+56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) # EH_FRAME_GEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) # EH_FRAME_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) # EH_FRAME_VMX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .balign 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .Lfde0_end:
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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