^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Signal trampolines for 32 bits processes in a ppc64 kernel for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * use in the vDSO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <asm/unistd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <asm/vdso.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* The nop here is a hack. The dwarf2 unwind routines subtract 1 from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) the return address to get an address in the middle of the presumed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) call instruction. Since we don't have a call here, we artificially
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) extend the range covered by the unwind info by adding a nop before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) the real start. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) V_FUNCTION_BEGIN(__kernel_sigtramp32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) .Lsig_start = . - 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) li r0,__NR_sigreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) sc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) .Lsig_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) V_FUNCTION_END(__kernel_sigtramp32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) .Lsigrt_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) nop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) li r0,__NR_rt_sigreturn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) sc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) .Lsigrt_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) V_FUNCTION_END(__kernel_sigtramp_rt32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) .section .eh_frame,"a",@progbits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Register r1 can be found at offset 4 of a pt_regs structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define cfa_save \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .byte 0x0f; /* DW_CFA_def_cfa_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) .byte 0x23; .uleb128 RSIZE; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Register REGNO can be found at offset OFS of a pt_regs structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) A pointer to the pt_regs is stored in memory at the old sp plus PTREGS. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define rsave(regno, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) .uleb128 regno; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .ifne ofs; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .endif; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) of the VMX reg struct. The VMX reg struct is at offset VREGS of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) the pt_regs struct. This macro is for REGNO == 0, and contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 'subroutines' that the other macros jump to. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define vsave_msr0(regno) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .byte 0x30 + regno; /* DW_OP_lit0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 2: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .byte 0x40; /* DW_OP_lit16 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .byte 0x1e; /* DW_OP_mul */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 3: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .byte 0x12; /* DW_OP_dup */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .byte 0x23; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .uleb128 33*RSIZE; /* msr offset */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .byte 0x0c; .long 1 << 25; /* DW_OP_const4u */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .byte 0x1a; /* DW_OP_and */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .byte 0x12; /* DW_OP_dup, ret 0 if bra taken */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .byte 0x30; /* DW_OP_lit0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .byte 0x29; /* DW_OP_eq */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .byte 0x28; .short 0x7fff; /* DW_OP_bra to end */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .byte 0x13; /* DW_OP_drop, pop the 0 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .byte 0x22; /* DW_OP_plus */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .byte 0x2f; .short 0x7fff; /* DW_OP_skip to end */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) of the VMX reg struct. REGNO is 1 thru 31. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define vsave_msr1(regno) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .byte 0x30 + regno; /* DW_OP_lit n */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .byte 0x2f; .short 2b - 9f; /* DW_OP_skip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) the VMX save block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define vsave_msr2(regno, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .byte 0x0a; .short ofs; /* DW_OP_const2u */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .byte 0x2f; .short 3b - 9f; /* DW_OP_skip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* VMX register REGNO is at offset OFS of the VMX save area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define vsave(regno, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .byte 0x10; /* DW_CFA_expression */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .uleb128 regno + 77; /* regno */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .uleb128 9f - 1f; /* length */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 1: \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .byte 0x71; .sleb128 PTREGS; /* DW_OP_breg1 */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .byte 0x06; /* DW_OP_deref */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .byte 0x23; .uleb128 VREGS; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .byte 0x23; .uleb128 ofs; /* DW_OP_plus_uconst */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* This is where the pt_regs pointer can be found on the stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PTREGS 64+28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Size of regs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RSIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* This is the offset of the VMX regs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VREGS 48*RSIZE+34*8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Describe where general purpose regs are saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EH_FRAME_GEN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) cfa_save; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) rsave ( 0, 0*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) rsave ( 2, 2*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) rsave ( 3, 3*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rsave ( 4, 4*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) rsave ( 5, 5*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rsave ( 6, 6*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rsave ( 7, 7*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) rsave ( 8, 8*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) rsave ( 9, 9*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) rsave (10, 10*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) rsave (11, 11*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rsave (12, 12*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rsave (13, 13*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rsave (14, 14*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) rsave (15, 15*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rsave (16, 16*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) rsave (17, 17*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rsave (18, 18*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) rsave (19, 19*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) rsave (20, 20*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rsave (21, 21*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) rsave (22, 22*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) rsave (23, 23*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) rsave (24, 24*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) rsave (25, 25*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) rsave (26, 26*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) rsave (27, 27*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rsave (28, 28*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) rsave (29, 29*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) rsave (30, 30*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) rsave (31, 31*RSIZE); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) rsave (67, 32*RSIZE); /* ap, used as temp for nip */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) rsave (65, 36*RSIZE); /* lr */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rsave (70, 38*RSIZE) /* cr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Describe where the FP regs are saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EH_FRAME_FP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) rsave (32, 48*RSIZE + 0*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) rsave (33, 48*RSIZE + 1*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rsave (34, 48*RSIZE + 2*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) rsave (35, 48*RSIZE + 3*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) rsave (36, 48*RSIZE + 4*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) rsave (37, 48*RSIZE + 5*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) rsave (38, 48*RSIZE + 6*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) rsave (39, 48*RSIZE + 7*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) rsave (40, 48*RSIZE + 8*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) rsave (41, 48*RSIZE + 9*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) rsave (42, 48*RSIZE + 10*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) rsave (43, 48*RSIZE + 11*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) rsave (44, 48*RSIZE + 12*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) rsave (45, 48*RSIZE + 13*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) rsave (46, 48*RSIZE + 14*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) rsave (47, 48*RSIZE + 15*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) rsave (48, 48*RSIZE + 16*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) rsave (49, 48*RSIZE + 17*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) rsave (50, 48*RSIZE + 18*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rsave (51, 48*RSIZE + 19*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) rsave (52, 48*RSIZE + 20*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) rsave (53, 48*RSIZE + 21*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) rsave (54, 48*RSIZE + 22*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) rsave (55, 48*RSIZE + 23*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) rsave (56, 48*RSIZE + 24*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) rsave (57, 48*RSIZE + 25*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) rsave (58, 48*RSIZE + 26*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) rsave (59, 48*RSIZE + 27*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) rsave (60, 48*RSIZE + 28*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rsave (61, 48*RSIZE + 29*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) rsave (62, 48*RSIZE + 30*8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) rsave (63, 48*RSIZE + 31*8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Describe where the VMX regs are saved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EH_FRAME_VMX \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) vsave_msr0 ( 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) vsave_msr1 ( 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) vsave_msr1 ( 2); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) vsave_msr1 ( 3); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) vsave_msr1 ( 4); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) vsave_msr1 ( 5); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) vsave_msr1 ( 6); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) vsave_msr1 ( 7); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) vsave_msr1 ( 8); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) vsave_msr1 ( 9); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) vsave_msr1 (10); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) vsave_msr1 (11); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) vsave_msr1 (12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) vsave_msr1 (13); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) vsave_msr1 (14); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) vsave_msr1 (15); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) vsave_msr1 (16); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) vsave_msr1 (17); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) vsave_msr1 (18); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) vsave_msr1 (19); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) vsave_msr1 (20); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) vsave_msr1 (21); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) vsave_msr1 (22); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) vsave_msr1 (23); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) vsave_msr1 (24); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) vsave_msr1 (25); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) vsave_msr1 (26); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) vsave_msr1 (27); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) vsave_msr1 (28); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) vsave_msr1 (29); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) vsave_msr1 (30); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) vsave_msr1 (31); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) vsave_msr2 (33, 32*16+12); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) vsave (32, 32*16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EH_FRAME_VMX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .Lcie:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .long .Lcie_end - .Lcie_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .Lcie_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .long 0 /* CIE ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .byte 1 /* Version number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .string "zRS" /* NUL-terminated augmentation string */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .uleb128 4 /* Code alignment factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .sleb128 -4 /* Data alignment factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .byte 67 /* Return address register column, ap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .uleb128 1 /* Augmentation value length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .byte 0x1b /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .byte 0x0c,1,0 /* DW_CFA_def_cfa: r1 ofs 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .Lcie_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .long .Lfde0_end - .Lfde0_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .Lfde0_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .long .Lfde0_start - .Lcie /* CIE pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .long .Lsig_start - . /* PC start, length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .long .Lsig_end - .Lsig_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .uleb128 0 /* Augmentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) EH_FRAME_GEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) EH_FRAME_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) EH_FRAME_VMX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .Lfde0_end:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* We have a different stack layout for rt_sigreturn. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #undef PTREGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PTREGS 64+16+128+20+28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .long .Lfde1_end - .Lfde1_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .Lfde1_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .long .Lfde1_start - .Lcie /* CIE pointer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .long .Lsigrt_start - . /* PC start, length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .long .Lsigrt_end - .Lsigrt_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .uleb128 0 /* Augmentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) EH_FRAME_GEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) EH_FRAME_FP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) EH_FRAME_VMX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .balign 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .Lfde1_end:
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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