Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * udbg for NS16550 compatible serial ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2001-2005 PPC 64 Team, IBM Corp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/udbg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/reg_a2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) extern u8 real_readb(volatile u8 __iomem  *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) extern void real_writeb(u8 data, volatile u8 __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) extern u8 real_205_readb(volatile u8 __iomem  *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) extern void real_205_writeb(u8 data, volatile u8 __iomem *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define UART_RBR	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define UART_IER	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define UART_FCR	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define UART_LCR	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define UART_MCR	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define UART_LSR	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define UART_MSR	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define UART_SCR	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define UART_THR	UART_RBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define UART_IIR	UART_FCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define UART_DLL	UART_RBR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define UART_DLM	UART_IER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define UART_DLAB	UART_LCR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LSR_DR   0x01  /* Data ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LSR_OE   0x02  /* Overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LSR_PE   0x04  /* Parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LSR_FE   0x08  /* Framing error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LSR_BI   0x10  /* Break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LSR_THRE 0x20  /* Xmit holding register empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LSR_TEMT 0x40  /* Xmitter empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LSR_ERR  0x80  /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LCR_DLAB 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) static u8 (*udbg_uart_in)(unsigned int reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) static void (*udbg_uart_out)(unsigned int reg, u8 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) static void udbg_uart_flush(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	if (!udbg_uart_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	/* wait for idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	while ((udbg_uart_in(UART_LSR) & LSR_THRE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) static void udbg_uart_putc(char c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	if (!udbg_uart_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	if (c == '\n')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		udbg_uart_putc('\r');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	udbg_uart_flush();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	udbg_uart_out(UART_THR, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int udbg_uart_getc_poll(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	if (!udbg_uart_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	if (!(udbg_uart_in(UART_LSR) & LSR_DR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		return udbg_uart_in(UART_RBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) static int udbg_uart_getc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	if (!udbg_uart_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* wait for char */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	while (!(udbg_uart_in(UART_LSR) & LSR_DR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	return udbg_uart_in(UART_RBR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static void udbg_use_uart(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	udbg_putc = udbg_uart_putc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	udbg_flush = udbg_uart_flush;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	udbg_getc = udbg_uart_getc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	udbg_getc_poll = udbg_uart_getc_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) void udbg_uart_setup(unsigned int speed, unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	unsigned int dll, base_bauds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	if (!udbg_uart_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (clock == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		clock = 1843200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	if (speed == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		speed = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	base_bauds = clock / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	dll = base_bauds / speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	udbg_uart_out(UART_LCR, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	udbg_uart_out(UART_IER, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	udbg_uart_out(UART_IER, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	udbg_uart_out(UART_LCR, LCR_DLAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	udbg_uart_out(UART_DLL, dll & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	udbg_uart_out(UART_DLM, dll >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	/* 8 data, 1 stop, no parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	udbg_uart_out(UART_LCR, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* RTS/DTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	udbg_uart_out(UART_MCR, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	/* Clear & enable FIFOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	udbg_uart_out(UART_FCR, 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int udbg_probe_uart_speed(unsigned int clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	unsigned int dll, dlm, divisor, prescaler, speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 old_lcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	old_lcr = udbg_uart_in(UART_LCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* select divisor latch registers.  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	udbg_uart_out(UART_LCR, old_lcr | LCR_DLAB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* now, read the divisor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dll = udbg_uart_in(UART_DLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	dlm = udbg_uart_in(UART_DLM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	divisor = dlm << 8 | dll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	/* check prescaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (udbg_uart_in(UART_MCR) & 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		prescaler = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		prescaler = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* restore the LCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	udbg_uart_out(UART_LCR, old_lcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* calculate speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	speed = (clock / prescaler) / (divisor * 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	/* sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (speed > (clock / 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		speed = 9600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	return speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	unsigned char __iomem *mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	unsigned long pio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) } udbg_uart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static unsigned int udbg_uart_stride = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static u8 udbg_uart_in_pio(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return inb(udbg_uart.pio_base + (reg * udbg_uart_stride));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static void udbg_uart_out_pio(unsigned int reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	outb(data, udbg_uart.pio_base + (reg * udbg_uart_stride));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) void udbg_uart_init_pio(unsigned long port, unsigned int stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (!port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	udbg_uart.pio_base = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	udbg_uart_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	udbg_uart_in = udbg_uart_in_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	udbg_uart_out = udbg_uart_out_pio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	udbg_use_uart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u8 udbg_uart_in_mmio(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return in_8(udbg_uart.mmio_base + (reg * udbg_uart_stride));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void udbg_uart_out_mmio(unsigned int reg, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	out_8(udbg_uart.mmio_base + (reg * udbg_uart_stride), data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void udbg_uart_init_mmio(void __iomem *addr, unsigned int stride)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	udbg_uart.mmio_base = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	udbg_uart_stride = stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	udbg_uart_in = udbg_uart_in_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	udbg_uart_out = udbg_uart_out_mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	udbg_use_uart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #ifdef CONFIG_PPC_MAPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define UDBG_UART_MAPLE_ADDR	((void __iomem *)0xf40003f8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static u8 udbg_uart_in_maple(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	return real_readb(UDBG_UART_MAPLE_ADDR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void udbg_uart_out_maple(unsigned int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	real_writeb(val, UDBG_UART_MAPLE_ADDR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) void __init udbg_init_maple_realmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	udbg_uart_in = udbg_uart_in_maple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	udbg_uart_out = udbg_uart_out_maple;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	udbg_use_uart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif /* CONFIG_PPC_MAPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_PPC_PASEMI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define UDBG_UART_PAS_ADDR	((void __iomem *)0xfcff03f8UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static u8 udbg_uart_in_pas(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	return real_205_readb(UDBG_UART_PAS_ADDR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void udbg_uart_out_pas(unsigned int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	real_205_writeb(val, UDBG_UART_PAS_ADDR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void __init udbg_init_pas_realmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	udbg_uart_in = udbg_uart_in_pas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	udbg_uart_out = udbg_uart_out_pas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	udbg_use_uart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #endif /* CONFIG_PPC_PASEMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #ifdef CONFIG_PPC_EARLY_DEBUG_44x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #include <platforms/44x/44x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u8 udbg_uart_in_44x_as1(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	return as1_readb((void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void udbg_uart_out_44x_as1(unsigned int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	as1_writeb(val, (void __iomem *)PPC44x_EARLY_DEBUG_VIRTADDR + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void __init udbg_init_44x_as1(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	udbg_uart_in = udbg_uart_in_44x_as1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	udbg_uart_out = udbg_uart_out_44x_as1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	udbg_use_uart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #ifdef CONFIG_PPC_EARLY_DEBUG_40x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static u8 udbg_uart_in_40x(unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	return real_readb((void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			  + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static void udbg_uart_out_40x(unsigned int reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	real_writeb(val, (void __iomem *)CONFIG_PPC_EARLY_DEBUG_40x_PHYSADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		    + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) void __init udbg_init_40x_realmode(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	udbg_uart_in = udbg_uart_in_40x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	udbg_uart_out = udbg_uart_out_40x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	udbg_use_uart();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #endif /* CONFIG_PPC_EARLY_DEBUG_40x */