^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <linux/cpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/percpu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/nodemask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpumask.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/notifier.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <asm/current.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <asm/hvcall.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/prom.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/machdep.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <asm/smp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/pmc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <asm/idle.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/svm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "cacheinfo.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include "setup.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <asm/paca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <asm/lppaca.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static DEFINE_PER_CPU(struct cpu, cpu_devices);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * 2014:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * up the kernel code."
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * code should be removed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static ssize_t store_smt_snooze_delay(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) current->comm, current->pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static ssize_t show_smt_snooze_delay(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) current->comm, current->pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return sprintf(buf, "100\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) store_smt_snooze_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) static int __init setup_smt_snooze_delay(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) if (!cpu_has_feature(CPU_FTR_SMT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) pr_warn("smt-snooze-delay command line option has no effect\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) __setup("smt-snooze-delay=", setup_smt_snooze_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void read_##NAME(void *val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *(unsigned long *)val = mfspr(ADDRESS); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void write_##NAME(void *val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) EXTRA; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) mtspr(ADDRESS, *(unsigned long *)val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static ssize_t show_##NAME(struct device *dev, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) char *buf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct cpu *cpu = container_of(dev, struct cpu, dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned long val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) return sprintf(buf, "%lx\n", val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static ssize_t __used \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) store_##NAME(struct device *dev, struct device_attribute *attr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) const char *buf, size_t count) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct cpu *cpu = container_of(dev, struct cpu, dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned long val; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret = sscanf(buf, "%lx", &val); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (ret != 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return -EINVAL; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return count; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SYSFS_PMCSETUP(NAME, ADDRESS) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) __SYSFS_SPRSETUP_SHOW_STORE(NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SYSFS_SPRSETUP(NAME, ADDRESS) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) __SYSFS_SPRSETUP_SHOW_STORE(NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) __SYSFS_SPRSETUP_SHOW_STORE(NAME)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * This is the system wide DSCR register default value. Any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * change to this default value through the sysfs interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * will update all per cpu DSCR default values across the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * system stored in their respective PACA structures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static unsigned long dscr_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * read_dscr() - Fetch the cpu specific DSCR default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @val: Returned cpu specific DSCR default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * This function returns the per cpu DSCR default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * for any cpu which is contained in it's PACA structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void read_dscr(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *(unsigned long *)val = get_paca()->dscr_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * write_dscr() - Update the cpu specific DSCR default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * @val: New cpu specific DSCR default value to update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * This function updates the per cpu DSCR default value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * for any cpu which is contained in it's PACA structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void write_dscr(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) get_paca()->dscr_default = *(unsigned long *)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!current->thread.dscr_inherit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) current->thread.dscr = *(unsigned long *)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) mtspr(SPRN_DSCR, *(unsigned long *)val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) SYSFS_SPRSETUP_SHOW_STORE(dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static void add_write_permission_dev_attr(struct device_attribute *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) attr->attr.mode |= 0200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * show_dscr_default() - Fetch the system wide DSCR default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @dev: Device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @attr: Device attribute structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @buf: Interface buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * This function returns the system wide DSCR default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static ssize_t show_dscr_default(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return sprintf(buf, "%lx\n", dscr_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * store_dscr_default() - Update the system wide DSCR default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @dev: Device structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @attr: Device attribute structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @buf: Interface buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @count: Size of the update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * This function updates the system wide DSCR default value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static ssize_t __used store_dscr_default(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ret = sscanf(buf, "%lx", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ret != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dscr_default = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) on_each_cpu(write_dscr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static DEVICE_ATTR(dscr_default, 0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) show_dscr_default, store_dscr_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static void sysfs_create_dscr_default(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (cpu_has_feature(CPU_FTR_DSCR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) dscr_default = spr_default_dscr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) for_each_possible_cpu(cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) paca_ptrs[cpu]->dscr_default = dscr_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MAX_BIT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static u64 pw20_wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static u64 altivec_idle_wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static unsigned int get_idle_ticks_bit(u64 ns)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u64 cycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (ns >= 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cycle = div_u64(ns * tb_ticks_per_usec, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!cycle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ilog2(cycle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void do_show_pwrmgtcr0(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) *value = mfspr(SPRN_PWRMGTCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static ssize_t show_pw20_state(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) value &= PWRMGTCR0_PW20_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return sprintf(buf, "%u\n", value ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static void do_store_pw20_state(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 pw20_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pw20_state = mfspr(SPRN_PWRMGTCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (*value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) pw20_state |= PWRMGTCR0_PW20_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) pw20_state &= ~PWRMGTCR0_PW20_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mtspr(SPRN_PWRMGTCR0, pw20_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static ssize_t store_pw20_state(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (kstrtou32(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (value > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static ssize_t show_pw20_wait_time(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u64 tb_cycle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u64 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (!pw20_wt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) value = (value & PWRMGTCR0_PW20_ENT) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PWRMGTCR0_PW20_ENT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* convert ms to ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (tb_ticks_per_usec > 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 rem_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) &rem_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) time = pw20_wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return sprintf(buf, "%llu\n", time > 0 ? time : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void set_pw20_wait_entry_bit(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 pw20_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) pw20_idle = mfspr(SPRN_PWRMGTCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Set Automatic PW20 Core Idle Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* clear count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pw20_idle &= ~PWRMGTCR0_PW20_ENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* set count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) mtspr(SPRN_PWRMGTCR0, pw20_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static ssize_t store_pw20_wait_time(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u32 entry_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (kstrtou64(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) entry_bit = get_idle_ticks_bit(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (entry_bit > MAX_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pw20_wt = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) smp_call_function_single(cpu, set_pw20_wait_entry_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) &entry_bit, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static ssize_t show_altivec_idle(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) value &= PWRMGTCR0_AV_IDLE_PD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return sprintf(buf, "%u\n", value ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static void do_store_altivec_idle(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 altivec_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) altivec_idle = mfspr(SPRN_PWRMGTCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (*value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mtspr(SPRN_PWRMGTCR0, altivec_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static ssize_t store_altivec_idle(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (kstrtou32(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (value > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static ssize_t show_altivec_idle_wait_time(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u64 tb_cycle = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u64 time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!altivec_idle_wt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PWRMGTCR0_AV_IDLE_CNT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* convert ms to ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (tb_ticks_per_usec > 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) u32 rem_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) &rem_us);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) time = altivec_idle_wt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return sprintf(buf, "%llu\n", time > 0 ? time : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) static void set_altivec_idle_wait_entry_bit(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 *value = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 altivec_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) altivec_idle = mfspr(SPRN_PWRMGTCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Set Automatic AltiVec Idle Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* clear count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* set count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) mtspr(SPRN_PWRMGTCR0, altivec_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static ssize_t store_altivec_idle_wait_time(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 entry_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u64 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int cpu = dev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (kstrtou64(buf, 0, &value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (!value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) entry_bit = get_idle_ticks_bit(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (entry_bit > MAX_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) altivec_idle_wt = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) &entry_bit, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Enable/Disable interface:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * 0, disable. 1, enable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) * Set wait time interface:(Nanosecond)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * Example: Base on TBfreq is 41MHZ.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) * 1~48(ns): TB[63]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * 49~97(ns): TB[62]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * 98~195(ns): TB[61]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * 196~390(ns): TB[60]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * 391~780(ns): TB[59]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * 781~1560(ns): TB[58]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static DEVICE_ATTR(pw20_wait_time, 0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) show_pw20_wait_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) store_pw20_wait_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static DEVICE_ATTR(altivec_idle_wait_time, 0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) show_altivec_idle_wait_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) store_altivec_idle_wait_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * Enabling PMCs will slow partition context switch times so we only do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * it the first time we write to the PMCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static DEFINE_PER_CPU(char, pmcs_enabled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) void ppc_enable_pmcs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ppc_set_pmu_inuse(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Only need to enable them once */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (__this_cpu_read(pmcs_enabled))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __this_cpu_write(pmcs_enabled, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (ppc_md.enable_pmcs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ppc_md.enable_pmcs();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) EXPORT_SYMBOL(ppc_enable_pmcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Let's define all possible registers, we'll only hook up the ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * that are implemented on the current processor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #ifdef CONFIG_PMU_SYSFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define HAS_PPC_PMC_CLASSIC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define HAS_PPC_PMC_IBM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define HAS_PPC_PMC_PA6T 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HAS_PPC_PMC56 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #ifdef CONFIG_PPC_BOOK3S_32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define HAS_PPC_PMC_G4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #endif /* CONFIG_PMU_SYSFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define HAS_PPC_PA6T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * SPRs which are not related to PMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) SYSFS_SPRSETUP(purr, SPRN_PURR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) SYSFS_SPRSETUP(spurr, SPRN_SPURR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) SYSFS_SPRSETUP(pir, SPRN_PIR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) SYSFS_SPRSETUP(tscr, SPRN_TSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) Lets only enable read for phyp resources and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) enable write when needed with a separate function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) Lets be conservative and default to pseries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static DEVICE_ATTR(pir, 0400, show_pir, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #ifdef HAS_PPC_PMC_CLASSIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #ifdef HAS_PPC_PMC_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #ifdef HAS_PPC_PMC56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #endif /* HAS_PPC_PMC56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #ifdef HAS_PPC_PMC_PA6T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #ifdef HAS_PPC_PA6T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) SYSFS_SPRSETUP(hid0, SPRN_HID0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) SYSFS_SPRSETUP(hid1, SPRN_HID1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) SYSFS_SPRSETUP(hid4, SPRN_HID4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) SYSFS_SPRSETUP(hid5, SPRN_HID5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #endif /* HAS_PPC_PA6T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #ifdef HAS_PPC_PMC_IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static struct device_attribute ibm_common_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #endif /* HAS_PPC_PMC_IBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #ifdef HAS_PPC_PMC_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static struct device_attribute g4_common_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #endif /* HAS_PPC_PMC_G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #ifdef HAS_PPC_PMC_CLASSIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static struct device_attribute classic_pmc_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #ifdef HAS_PPC_PMC56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static struct device_attribute pa6t_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #ifdef HAS_PPC_PMC_PA6T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #ifdef HAS_PPC_PA6T
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) __ATTR(hid0, 0600, show_hid0, store_hid0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) __ATTR(hid1, 0600, show_hid1, store_hid1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) __ATTR(hid4, 0600, show_hid4, store_hid4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) __ATTR(hid5, 0600, show_hid5, store_hid5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) __ATTR(ima0, 0600, show_ima0, store_ima0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) __ATTR(ima1, 0600, show_ima1, store_ima1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) __ATTR(ima2, 0600, show_ima2, store_ima2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) __ATTR(ima3, 0600, show_ima3, store_ima3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) __ATTR(ima4, 0600, show_ima4, store_ima4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __ATTR(ima5, 0600, show_ima5, store_ima5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) __ATTR(ima6, 0600, show_ima6, store_ima6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __ATTR(ima7, 0600, show_ima7, store_ima7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __ATTR(ima8, 0600, show_ima8, store_ima8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) __ATTR(ima9, 0600, show_ima9, store_ima9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) __ATTR(imaat, 0600, show_imaat, store_imaat),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) __ATTR(btcr, 0600, show_btcr, store_btcr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) __ATTR(pccr, 0600, show_pccr, store_pccr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) __ATTR(der, 0600, show_der, store_der),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __ATTR(mer, 0600, show_mer, store_mer),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) __ATTR(ber, 0600, show_ber, store_ber),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __ATTR(ier, 0600, show_ier, store_ier),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __ATTR(sier, 0600, show_sier, store_sier),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) __ATTR(siar, 0600, show_siar, store_siar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif /* HAS_PPC_PA6T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #ifdef CONFIG_PPC_SVM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return sprintf(buf, "%u\n", is_secure_guest());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static DEVICE_ATTR(svm, 0444, show_svm, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static void create_svm_file(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static void create_svm_file(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #endif /* CONFIG_PPC_SVM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) #ifdef CONFIG_PPC_PSERIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void read_idle_purr(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u64 *ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *ret = read_this_idle_purr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static ssize_t idle_purr_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct cpu *cpu = container_of(dev, struct cpu, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return sprintf(buf, "%llx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static void create_idle_purr_file(struct device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) device_create_file(s, &dev_attr_idle_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void remove_idle_purr_file(struct device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) device_remove_file(s, &dev_attr_idle_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void read_idle_spurr(void *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u64 *ret = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *ret = read_this_idle_spurr();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static ssize_t idle_spurr_show(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct cpu *cpu = container_of(dev, struct cpu, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return sprintf(buf, "%llx\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void create_idle_spurr_file(struct device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) device_create_file(s, &dev_attr_idle_spurr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static void remove_idle_spurr_file(struct device *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) device_remove_file(s, &dev_attr_idle_spurr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #else /* CONFIG_PPC_PSERIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define create_idle_purr_file(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define remove_idle_purr_file(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define create_idle_spurr_file(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define remove_idle_spurr_file(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #endif /* CONFIG_PPC_PSERIES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int register_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct cpu *c = &per_cpu(cpu_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct device *s = &c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct device_attribute *attrs, *pmc_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int i, nattrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* For cpus present at boot a reference was already grabbed in register_cpu() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (!s->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) s->of_node = of_get_cpu_node(cpu, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (cpu_has_feature(CPU_FTR_SMT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) device_create_file(s, &dev_attr_smt_snooze_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* PMC stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) switch (cur_cpu_spec->pmc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #ifdef HAS_PPC_PMC_IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case PPC_PMC_IBM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) attrs = ibm_common_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pmc_attrs = classic_pmc_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #endif /* HAS_PPC_PMC_IBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #ifdef HAS_PPC_PMC_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) case PPC_PMC_G4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) attrs = g4_common_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pmc_attrs = classic_pmc_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #endif /* HAS_PPC_PMC_G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case PPC_PMC_PA6T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) /* PA Semi starts counting at PMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) attrs = pa6t_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) pmc_attrs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) attrs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) nattrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pmc_attrs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) for (i = 0; i < nattrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) device_create_file(s, &attrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (pmc_attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) device_create_file(s, &pmc_attrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #ifdef CONFIG_PMU_SYSFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (cpu_has_feature(CPU_FTR_MMCRA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) device_create_file(s, &dev_attr_mmcra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (cpu_has_feature(CPU_FTR_ARCH_31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) device_create_file(s, &dev_attr_mmcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #endif /* CONFIG_PMU_SYSFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) if (cpu_has_feature(CPU_FTR_PURR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) add_write_permission_dev_attr(&dev_attr_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) device_create_file(s, &dev_attr_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) create_idle_purr_file(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (cpu_has_feature(CPU_FTR_SPURR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) device_create_file(s, &dev_attr_spurr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) create_idle_spurr_file(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (cpu_has_feature(CPU_FTR_DSCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) device_create_file(s, &dev_attr_dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) device_create_file(s, &dev_attr_pir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (cpu_has_feature(CPU_FTR_ARCH_206) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) !firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) device_create_file(s, &dev_attr_tscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) device_create_file(s, &dev_attr_pw20_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) device_create_file(s, &dev_attr_pw20_wait_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) device_create_file(s, &dev_attr_altivec_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) device_create_file(s, &dev_attr_altivec_idle_wait_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) cacheinfo_cpu_online(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int unregister_cpu_online(unsigned int cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct cpu *c = &per_cpu(cpu_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct device *s = &c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct device_attribute *attrs, *pmc_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) int i, nattrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) BUG_ON(!c->hotpluggable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (cpu_has_feature(CPU_FTR_SMT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) device_remove_file(s, &dev_attr_smt_snooze_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* PMC stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) switch (cur_cpu_spec->pmc_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #ifdef HAS_PPC_PMC_IBM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case PPC_PMC_IBM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) attrs = ibm_common_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pmc_attrs = classic_pmc_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #endif /* HAS_PPC_PMC_IBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #ifdef HAS_PPC_PMC_G4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case PPC_PMC_G4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) attrs = g4_common_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pmc_attrs = classic_pmc_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #endif /* HAS_PPC_PMC_G4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) case PPC_PMC_PA6T:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* PA Semi starts counting at PMC0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) attrs = pa6t_attrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) pmc_attrs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) attrs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) nattrs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) pmc_attrs = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) for (i = 0; i < nattrs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) device_remove_file(s, &attrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (pmc_attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) device_remove_file(s, &pmc_attrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #ifdef CONFIG_PMU_SYSFS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (cpu_has_feature(CPU_FTR_MMCRA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) device_remove_file(s, &dev_attr_mmcra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (cpu_has_feature(CPU_FTR_ARCH_31))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) device_remove_file(s, &dev_attr_mmcr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #endif /* CONFIG_PMU_SYSFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (cpu_has_feature(CPU_FTR_PURR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) device_remove_file(s, &dev_attr_purr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) remove_idle_purr_file(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (cpu_has_feature(CPU_FTR_SPURR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) device_remove_file(s, &dev_attr_spurr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) remove_idle_spurr_file(s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (cpu_has_feature(CPU_FTR_DSCR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) device_remove_file(s, &dev_attr_dscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) device_remove_file(s, &dev_attr_pir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (cpu_has_feature(CPU_FTR_ARCH_206) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) !firmware_has_feature(FW_FEATURE_LPAR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) device_remove_file(s, &dev_attr_tscr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #ifdef CONFIG_PPC_FSL_BOOK3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) device_remove_file(s, &dev_attr_pw20_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) device_remove_file(s, &dev_attr_pw20_wait_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) device_remove_file(s, &dev_attr_altivec_idle);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) device_remove_file(s, &dev_attr_altivec_idle_wait_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) cacheinfo_cpu_offline(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) of_node_put(s->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) s->of_node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #else /* !CONFIG_HOTPLUG_CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define unregister_cpu_online NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ssize_t arch_cpu_probe(const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (ppc_md.cpu_probe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return ppc_md.cpu_probe(buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ssize_t arch_cpu_release(const char *buf, size_t count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ppc_md.cpu_release)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ppc_md.cpu_release(buf, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static DEFINE_MUTEX(cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) int cpu_add_dev_attr(struct device_attribute *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) mutex_lock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) device_create_file(get_cpu_device(cpu), attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mutex_unlock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int cpu_add_dev_attr_group(struct attribute_group *attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_lock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = sysfs_create_group(&dev->kobj, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) WARN_ON(ret != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) mutex_unlock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) void cpu_remove_dev_attr(struct device_attribute *attr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mutex_lock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) device_remove_file(get_cpu_device(cpu), attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) mutex_unlock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) void cpu_remove_dev_attr_group(struct attribute_group *attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mutex_lock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dev = get_cpu_device(cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) sysfs_remove_group(&dev->kobj, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) mutex_unlock(&cpu_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* NUMA stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #ifdef CONFIG_NUMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static void register_nodes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) for (i = 0; i < MAX_NUMNODES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) register_one_node(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int sysfs_add_device_to_node(struct device *dev, int nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct node *node = node_devices[nid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return sysfs_create_link(&node->dev.kobj, &dev->kobj,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) kobject_name(&dev->kobj));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) void sysfs_remove_device_from_node(struct device *dev, int nid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct node *node = node_devices[nid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static void register_nodes(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Only valid if CPU is present. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static ssize_t show_physical_id(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct device_attribute *attr, char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct cpu *cpu = container_of(dev, struct cpu, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int __init topology_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) int cpu, r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) register_nodes();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) for_each_possible_cpu(cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct cpu *c = &per_cpu(cpu_devices, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #ifdef CONFIG_HOTPLUG_CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) * For now, we just see if the system supports making
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) * the RTAS calls for CPU hotplug. But, there may be a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * more comprehensive way to do this for an individual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * CPU. For instance, the boot cpu might never be valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) * for hotplugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (smp_ops && smp_ops->cpu_offline_self)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) c->hotpluggable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (cpu_online(cpu) || c->hotpluggable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) register_cpu(c, cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) device_create_file(&c->dev, &dev_attr_physical_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) register_cpu_online, unregister_cpu_online);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) WARN_ON(r < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #ifdef CONFIG_PPC64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sysfs_create_dscr_default();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #endif /* CONFIG_PPC64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) create_svm_file();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) subsys_initcall(topology_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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