Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * PowerPC 64-bit swsusp implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * Structure for storing CPU registers on the save area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SL_r1		0x00	/* stack pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SL_PC		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SL_MSR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SL_SDR1		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SL_XER		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SL_TB		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SL_r2		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SL_CR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SL_LR		0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SL_r12		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SL_r13		0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SL_r14		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SL_r15		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SL_r16		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SL_r17		0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SL_r18		0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SL_r19		0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SL_r20		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SL_r21		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SL_r22		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SL_r23		0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SL_r24		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SL_r25		0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SL_r26		0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SL_r27		0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SL_r28		0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SL_r29		0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SL_r30		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SL_r31		0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SL_SPRG1	0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SL_TCR		0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SL_SIZE		SL_TCR+8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* these macros rely on the save area being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * pointed to by r11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SAVE_SPR(register)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	mfspr	r0, SPRN_##register	;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	std	r0, SL_##register(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define RESTORE_SPR(register)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	ld	r0, SL_##register(r11)	;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	mtspr	SPRN_##register, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SAVE_SPECIAL(special)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	mf##special	r0		;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	std	r0, SL_##special(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define RESTORE_SPECIAL(special)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	ld	r0, SL_##special(r11)	;\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mt##special	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SAVE_REGISTER(reg)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	std	reg, SL_##reg(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define RESTORE_REGISTER(reg)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	ld	reg, SL_##reg(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* space for storing cpu state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.section .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	.align  5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) swsusp_save_area:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	.space SL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	.section ".toc","aw"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) swsusp_save_area_ptr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.tc	swsusp_save_area[TC],swsusp_save_area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) restore_pblist_ptr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.tc	restore_pblist[TC],restore_pblist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.section .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.align  5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) _GLOBAL(swsusp_arch_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	ld	r11,swsusp_save_area_ptr@toc(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	SAVE_SPECIAL(LR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	SAVE_REGISTER(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	SAVE_SPECIAL(CR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	SAVE_SPECIAL(TB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	SAVE_REGISTER(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	SAVE_REGISTER(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	SAVE_REGISTER(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	SAVE_REGISTER(r14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	SAVE_REGISTER(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	SAVE_REGISTER(r16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	SAVE_REGISTER(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	SAVE_REGISTER(r18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	SAVE_REGISTER(r19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	SAVE_REGISTER(r20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	SAVE_REGISTER(r21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	SAVE_REGISTER(r22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	SAVE_REGISTER(r23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	SAVE_REGISTER(r24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	SAVE_REGISTER(r25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	SAVE_REGISTER(r26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	SAVE_REGISTER(r27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	SAVE_REGISTER(r28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	SAVE_REGISTER(r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	SAVE_REGISTER(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	SAVE_REGISTER(r31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	SAVE_SPECIAL(MSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	SAVE_SPECIAL(XER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) BEGIN_FW_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	SAVE_SPECIAL(SDR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) END_FW_FTR_SECTION_IFCLR(FW_FEATURE_LPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	SAVE_SPR(TCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	/* Save SPRG1, SPRG1 be used save paca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	SAVE_SPR(SPRG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* we push the stack up 128 bytes but don't store the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	 * stack pointer on the stack like a real stackframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	addi	r1,r1,-128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	bl _iommu_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	bl swsusp_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* restore LR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	ld	r11,swsusp_save_area_ptr@toc(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	RESTORE_SPECIAL(LR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	addi	r1,r1,128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Resume code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) _GLOBAL(swsusp_arch_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Stop pending alitvec streams and memory accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	DSSALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	ld	r12,restore_pblist_ptr@toc(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	ld	r12,0(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	cmpdi	r12,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	beq-	nothing_to_copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	li	r15,PAGE_SIZE>>3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) copyloop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	ld	r13,pbe_address(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	ld	r14,pbe_orig_address(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	mtctr	r15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	li	r10,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) copy_page_loop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	ldx	r0,r10,r13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	stdx	r0,r10,r14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	addi	r10,r10,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	bdnz copy_page_loop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	ld	r12,pbe_next(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	cmpdi	r12,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	bne+	copyloop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) nothing_to_copy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* flush caches */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	lis	r3, 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	mtctr	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ori	r3, r3, CONFIG_KERNEL_START>>48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	li	r0, 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	sld	r3, r3, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	li	r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	dcbf	0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	addi	r3,r3,0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	bdnz	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	tlbia
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	ld	r11,swsusp_save_area_ptr@toc(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	RESTORE_SPECIAL(CR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	/* restore timebase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	/* load saved tb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ld	r1, SL_TB(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	/* get upper 32 bits of it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	srdi	r2, r1, 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* clear tb lower to avoid wrap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	li	r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	mttbl	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	/* set tb upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mttbu	r2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/* set tb lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	mttbl	r1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* restore registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	RESTORE_REGISTER(r1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	RESTORE_REGISTER(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	RESTORE_REGISTER(r12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	RESTORE_REGISTER(r13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	RESTORE_REGISTER(r14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	RESTORE_REGISTER(r15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	RESTORE_REGISTER(r16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	RESTORE_REGISTER(r17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	RESTORE_REGISTER(r18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	RESTORE_REGISTER(r19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	RESTORE_REGISTER(r20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	RESTORE_REGISTER(r21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	RESTORE_REGISTER(r22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	RESTORE_REGISTER(r23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	RESTORE_REGISTER(r24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	RESTORE_REGISTER(r25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	RESTORE_REGISTER(r26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	RESTORE_REGISTER(r27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	RESTORE_REGISTER(r28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	RESTORE_REGISTER(r29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	RESTORE_REGISTER(r30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	RESTORE_REGISTER(r31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	/* can't use RESTORE_SPECIAL(MSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	ld	r0, SL_MSR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mtmsrd	r0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) BEGIN_FW_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	RESTORE_SPECIAL(SDR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) END_FW_FTR_SECTION_IFCLR(FW_FEATURE_LPAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* Restore SPRG1, be used to save paca */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ld	r0, SL_SPRG1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mtsprg	1, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	RESTORE_SPECIAL(MSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* Restore TCR and clear any pending bits in TSR. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	RESTORE_SPR(TCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	lis	r0, (TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	mtspr	SPRN_TSR, r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	/* Kick decrementer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	li	r0, 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	mtdec	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	/* Invalidate all tlbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	bl	_tlbil_all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	RESTORE_SPECIAL(XER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	addi	r1,r1,-128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #ifdef CONFIG_PPC_BOOK3S_64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	bl	slb_flush_and_restore_bolted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	bl	do_after_copyback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	addi	r1,r1,128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	ld	r11,swsusp_save_area_ptr@toc(r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	RESTORE_SPECIAL(LR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	blr