Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) #include <linux/threads.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <asm/processor.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <asm/cputable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <asm/thread_info.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <asm/ppc_asm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <asm/asm-offsets.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <asm/mmu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <asm/feature-fixups.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Structure for storing CPU registers on the save area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define SL_SP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SL_PC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SL_MSR		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SL_SDR1		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SL_SPRG0	0x10	/* 4 sprg's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SL_DBAT0	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SL_IBAT0	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SL_DBAT1	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SL_IBAT1	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SL_DBAT2	0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SL_IBAT2	0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SL_DBAT3	0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SL_IBAT3	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SL_DBAT4	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SL_IBAT4	0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SL_DBAT5	0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SL_IBAT5	0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SL_DBAT6	0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SL_IBAT6	0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SL_DBAT7	0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SL_IBAT7	0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SL_TB		0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SL_R2		0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SL_CR		0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SL_LR		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SL_R12		0xb4	/* r12 to r31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SL_SIZE		(SL_R12 + 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	.section .data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) _GLOBAL(swsusp_save_area)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	.space	SL_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	.section .text
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	.align	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) _GLOBAL(swsusp_arch_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	lis	r11,swsusp_save_area@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	ori	r11,r11,swsusp_save_area@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	mflr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	stw	r0,SL_LR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	mfcr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	stw	r0,SL_CR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	stw	r1,SL_SP(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	stw	r2,SL_R2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	stmw	r12,SL_R12(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	/* Save MSR & SDR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	mfmsr	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	stw	r4,SL_MSR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	mfsdr1	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	stw	r4,SL_SDR1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* Get a stable timebase and save it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 1:	mftbu	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	stw	r4,SL_TB(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	mftb	r5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	stw	r5,SL_TB+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	mftbu	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	cmpw	r3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	bne	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	/* Save SPRGs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	mfsprg	r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	stw	r4,SL_SPRG0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	mfsprg	r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	stw	r4,SL_SPRG0+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	mfsprg	r4,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	stw	r4,SL_SPRG0+8(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	mfsprg	r4,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	stw	r4,SL_SPRG0+12(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* Save BATs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	mfdbatu	r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	stw	r4,SL_DBAT0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	mfdbatl	r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	stw	r4,SL_DBAT0+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	mfdbatu	r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	stw	r4,SL_DBAT1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	mfdbatl	r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	stw	r4,SL_DBAT1+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mfdbatu	r4,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	stw	r4,SL_DBAT2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	mfdbatl	r4,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	stw	r4,SL_DBAT2+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	mfdbatu	r4,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	stw	r4,SL_DBAT3(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	mfdbatl	r4,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	stw	r4,SL_DBAT3+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	mfibatu	r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	stw	r4,SL_IBAT0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	mfibatl	r4,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	stw	r4,SL_IBAT0+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	mfibatu	r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	stw	r4,SL_IBAT1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	mfibatl	r4,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	stw	r4,SL_IBAT1+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	mfibatu	r4,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	stw	r4,SL_IBAT2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	mfibatl	r4,2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	stw	r4,SL_IBAT2+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	mfibatu	r4,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	stw	r4,SL_IBAT3(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	mfibatl	r4,3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	stw	r4,SL_IBAT3+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) BEGIN_MMU_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	mfspr	r4,SPRN_DBAT4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	stw	r4,SL_DBAT4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	mfspr	r4,SPRN_DBAT4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	stw	r4,SL_DBAT4+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	mfspr	r4,SPRN_DBAT5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	stw	r4,SL_DBAT5(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	mfspr	r4,SPRN_DBAT5L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	stw	r4,SL_DBAT5+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mfspr	r4,SPRN_DBAT6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	stw	r4,SL_DBAT6(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	mfspr	r4,SPRN_DBAT6L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	stw	r4,SL_DBAT6+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	mfspr	r4,SPRN_DBAT7U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	stw	r4,SL_DBAT7(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	mfspr	r4,SPRN_DBAT7L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	stw	r4,SL_DBAT7+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	mfspr	r4,SPRN_IBAT4U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	stw	r4,SL_IBAT4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	mfspr	r4,SPRN_IBAT4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	stw	r4,SL_IBAT4+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	mfspr	r4,SPRN_IBAT5U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	stw	r4,SL_IBAT5(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	mfspr	r4,SPRN_IBAT5L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	stw	r4,SL_IBAT5+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	mfspr	r4,SPRN_IBAT6U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	stw	r4,SL_IBAT6(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	mfspr	r4,SPRN_IBAT6L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	stw	r4,SL_IBAT6+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	mfspr	r4,SPRN_IBAT7U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	stw	r4,SL_IBAT7(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	mfspr	r4,SPRN_IBAT7L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	stw	r4,SL_IBAT7+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #if  0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	/* Backup various CPU config stuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	bl	__save_cpu_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	/* Call the low level suspend stuff (we should probably have made
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	 * a stackframe...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	bl	swsusp_save
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Restore LR from the save area */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	lis	r11,swsusp_save_area@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	ori	r11,r11,swsusp_save_area@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	lwz	r0,SL_LR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Resume code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) _GLOBAL(swsusp_arch_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #ifdef CONFIG_ALTIVEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	/* Stop pending alitvec streams and memory accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BEGIN_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	DSSALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)  	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	/* Disable MSR:DR to make sure we don't take a TLB or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	 * hash miss during the copy, as our hash table will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	 * for a while be unusable. For .text, we assume we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	 * covered by a BAT. This works only for non-G5 at this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	 * point. G5 will need a better approach, possibly using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	 * a small temporary hash table filled with large mappings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	 * disabling the MMU completely isn't a good option for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	 * performance reasons.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	 * (Note that 750's may have the same performance issue as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	 * the G5 in this case, we should investigate using moving
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	 * BATs for these CPUs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	mfmsr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	rlwinm	r0,r0,0,28,26		/* clear MSR_DR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	mtmsr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	/* Load ptr the list of pages to copy in r3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	lis	r11,(restore_pblist - KERNELBASE)@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	ori	r11,r11,restore_pblist@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	lwz	r10,0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	/* Copy the pages. This is a very basic implementation, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	 * be replaced by something more cache efficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	tophys(r3,r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	li	r0,256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	mtctr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	lwz	r11,pbe_address(r3)	/* source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	tophys(r5,r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	lwz	r10,pbe_orig_address(r3)	/* destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	tophys(r6,r10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	lwz	r8,0(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	lwz	r9,4(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	lwz	r10,8(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	lwz	r11,12(r5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	addi	r5,r5,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	stw	r8,0(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	stw	r9,4(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	stw	r10,8(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	stw	r11,12(r6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	addi	r6,r6,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	bdnz	2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	lwz		r10,pbe_next(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	cmpwi	0,r10,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	bne	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	/* Do a very simple cache flush/inval of the L1 to ensure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	 * coherency of the icache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	lis	r3,0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	mtctr	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	lwz	r0,0(r3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	addi	r3,r3,0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	bdnz	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	/* Now flush those cache lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	lis	r3,0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	mtctr	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	li	r3, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	dcbf	0,r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	addi	r3,r3,0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	bdnz	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	/* Ok, we are now running with the kernel data of the old
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	 * kernel fully restored. We can get to the save area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	 * easily now. As for the rest of the code, it assumes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	 * loader kernel and the booted one are exactly identical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	lis	r11,swsusp_save_area@h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	ori	r11,r11,swsusp_save_area@l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	tophys(r11,r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	/* Restore various CPU config stuffs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	bl	__restore_cpu_setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	/* Restore the BATs, and SDR1.  Then we can turn on the MMU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	 * This is a bit hairy as we are running out of those BATs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	 * but first, our code is probably in the icache, and we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	 * writing the same value to the BAT, so that should be fine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	 * though a better solution will have to be found long-term
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	lwz	r4,SL_SDR1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	mtsdr1	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	lwz	r4,SL_SPRG0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	mtsprg	0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	lwz	r4,SL_SPRG0+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	mtsprg	1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	lwz	r4,SL_SPRG0+8(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	mtsprg	2,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	lwz	r4,SL_SPRG0+12(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	mtsprg	3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	lwz	r4,SL_DBAT0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	mtdbatu	0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	lwz	r4,SL_DBAT0+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	mtdbatl	0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	lwz	r4,SL_DBAT1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	mtdbatu	1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	lwz	r4,SL_DBAT1+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	mtdbatl	1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	lwz	r4,SL_DBAT2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	mtdbatu	2,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	lwz	r4,SL_DBAT2+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	mtdbatl	2,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	lwz	r4,SL_DBAT3(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	mtdbatu	3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	lwz	r4,SL_DBAT3+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	mtdbatl	3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	lwz	r4,SL_IBAT0(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	mtibatu	0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	lwz	r4,SL_IBAT0+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	mtibatl	0,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	lwz	r4,SL_IBAT1(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	mtibatu	1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	lwz	r4,SL_IBAT1+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	mtibatl	1,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	lwz	r4,SL_IBAT2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	mtibatu	2,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	lwz	r4,SL_IBAT2+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	mtibatl	2,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	lwz	r4,SL_IBAT3(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	mtibatu	3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	lwz	r4,SL_IBAT3+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	mtibatl	3,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) BEGIN_MMU_FTR_SECTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	lwz	r4,SL_DBAT4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	mtspr	SPRN_DBAT4U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	lwz	r4,SL_DBAT4+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	mtspr	SPRN_DBAT4L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	lwz	r4,SL_DBAT5(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	mtspr	SPRN_DBAT5U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	lwz	r4,SL_DBAT5+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	mtspr	SPRN_DBAT5L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	lwz	r4,SL_DBAT6(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	mtspr	SPRN_DBAT6U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	lwz	r4,SL_DBAT6+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	mtspr	SPRN_DBAT6L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	lwz	r4,SL_DBAT7(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	mtspr	SPRN_DBAT7U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	lwz	r4,SL_DBAT7+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	mtspr	SPRN_DBAT7L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	lwz	r4,SL_IBAT4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	mtspr	SPRN_IBAT4U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	lwz	r4,SL_IBAT4+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	mtspr	SPRN_IBAT4L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	lwz	r4,SL_IBAT5(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	mtspr	SPRN_IBAT5U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	lwz	r4,SL_IBAT5+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	mtspr	SPRN_IBAT5L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	lwz	r4,SL_IBAT6(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	mtspr	SPRN_IBAT6U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	lwz	r4,SL_IBAT6+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	mtspr	SPRN_IBAT6L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	lwz	r4,SL_IBAT7(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	mtspr	SPRN_IBAT7U,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	lwz	r4,SL_IBAT7+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	mtspr	SPRN_IBAT7L,r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	/* Flush all TLBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	lis	r4,0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 1:	addic.	r4,r4,-0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	tlbie	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	bgt	1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	/* restore the MSR and turn on the MMU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	lwz	r3,SL_MSR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	bl	turn_on_mmu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	tovirt(r11,r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	/* Restore TB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	li	r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	mttbl	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	lwz	r3,SL_TB(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	lwz	r4,SL_TB+4(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	mttbu	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	mttbl	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	/* Kick decrementer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	li	r0,1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	mtdec	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	/* Restore the callee-saved registers and return */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	lwz	r0,SL_CR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	mtcr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	lwz	r2,SL_R2(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	lmw	r12,SL_R12(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	lwz	r1,SL_SP(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	lwz	r0,SL_LR(r11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	mtlr	r0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	// XXX Note: we don't really need to call swsusp_resume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	li	r3,0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	blr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) _ASM_NOKPROBE_SYMBOL(swsusp_arch_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* FIXME:This construct is actually not useful since we don't shut
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)  * down the instruction MMU, we could just flip back MSR-DR on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) turn_on_mmu:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	mflr	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	mtsrr0	r4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	mtsrr1	r3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	sync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	isync
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	rfi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) _ASM_NOKPROBE_SYMBOL(turn_on_mmu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)